Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 108
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Trace Status Register
The Trace Status Register (TSR) can be used to determine if trace has been started or not, to
check for cycle count overflow and to read the sampled number of items in the Embedded
Trace Buffer. This register is a read-only register. Issuing a write request to the register does
nothing. See the following figure and table.
Trace Data Read Register
The Trace Data Read Register (TDRR) contains the oldest item read from the Embedded
Trace Buffer. When the register has been read, the next item is read from the trace buffer. It
is an error to read more items than are available in the trace buffer, as indicated by the item
count in the Trace Status Register. This register is a read-only register. Issuing a write request to
the register does nothing. See the following figure and table.
Table 2-51: Trace Command Register (TCMDR)
Bits Name Description Reset Value
3Clear
Clear trace status and empty the trace buffer
0
2Start
Start trace immediately
0
1Stop
Stop trace immediately
0
0Sample
Sample the number of current items in the trace buffer
0
X-Ref Target - Figure 2-33
Figure 2-33: Trace Status Register
0
Reserved
31 18
Item Count
17
STA
16
OF
15
X19769-082517
Table 2-52: Trace Status Register (TSR)
Bits Name Description Reset Value
17 Started
Trace started, set to one when trace is started and cleared to zero
when it is stopped
0
16 Overflow
Cycle count overflow, set to one when the cycle count overflows, and
cleared to zero by the Clear command
0
15:0 Item Count
Sampled trace buffer item count
0x0000
X-Ref Target - Figure 2-34
Figure 2-34: Trace Data Read Register
0
Reserved
31 18
Buffer Value
17
X19770-082517
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module