Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 109
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Because a trace data entity can consist of more than 18 bits, depending on the compression
level and stored data, the register might need to be read repeatedly to retrieve all
information for a particular data entity. This is detailed in
Table 2-54.
Table 2-53: Trace Data Read Register (TDRR)
Bits Name Description Reset Value
17:0 Buffer Value
Embedded Trace Buffer item
0x00000
Table 2-54: Trace Counter Data Entities
Entity Item Bits Description
Complete Trace 1 17:3
2:0
Cycle count for the executed instruction
Machine Status Register [17:19]
2 17:6
5:1
0
Machine Status Register [20:31]
Destination register address (r0 - r31), valid if written
Destination register written if set to one
3 17:13
12
11
10
9:6
5:0
Exception Kind, valid if exception taken
Exception taken if set to one
Load instruction reading data if set to one
Store instruction writing data if set to one
Byte enable, valid for store instruction
Write data [0:5] for store instructions, or Destination
register data [0:5] for other instructions
4 17:0 Write data [6:23] or Destination register data [6:23]
5 17:10
9:0
Write data [24:31] or Destination register data [24:31]
Data address [0:9] for load and store instructions, or
Executed instruction [0:9] for other instruction
6 17:0 Data address [10:27] or Executed instruction [10:27]
7 17:14
13:0
Data address [28:31] or Executed instruction [28:31]
Program Counter [0:13]
8 17:0 Program Counter [14:31]
Program Flow: Branches 1 17:16
15:12
11:0
00 - The item contains program flow branches
Number of branches (N) counted in the item (0 - 12)
The N leftmost bits represent branches in the
program flow. If the bit is set to one the branch is
taken, otherwise it is not taken.
An item with 0 branches can be ignored, and may
occur when flushing external trace, in order to
complete a trace packet.
Program Flow: Program Counter 1 17:16
15:0
01 - The item contains a Program Counter value
Program Counter [0:15]
2 17:16
15:0
01 - The item contains a Program Counter value
Program Counter [16:31]
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module