Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 30
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Exception Status Register (ESR)
The Exception Status Register contains status bits for the processor. When read with the
MFS instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated
in the following figure,
Table 2-11 provides bit descriptions and reset values, and Table 2-12
provides the Exception Specific Status (ESS).
Table 2-10: Exception Address Register (EAR)
Bits Name Description Reset Value
0:C_ADDR_SIZE-1 EAR Exception Address Register 0
X-Ref Target - Figure 2-6
Figure 2-6: ESR
31
EC
19
Reserved
2726
20
ESS
DS
X19743-082517
Table 2-11: Exception Status Register (ESR)
Bits Name Description Reset Value
0:18 Reserved
19 DS Delay Slot Exception.
0 = not caused by delay slot instruction
1 = caused by delay slot instruction
Read-only
0
20:26 ESS Exception Specific Status
For details, see Table 2-12.
Read-only
See
Table 2-12
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module