Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 110
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Program Flow: Read Data 1 17:16
15:0
10 - The item contains read data
Data read by load and get instructions [0:15]
2 17:16
15:0
10 - The item contains read data
Data read by load and get instructions [15:31]
Program Flow, Event: Event
Instruction event
1 17:16
15:14
13:0
11 – The item contains an event
00 – Instruction event
Software generated trace event: result of instruction
“xori r0, rA, IMM”.
Program Flow, Event: Event
Cross-trigger event
1 17:16
15:1
13:8
7:0
11 – The item contains an event
10 – Cross-trigger event
Reserved
Events according to “MicroBlaze Cross Trigger
Events” defined in
Table 2-63. Each event is
represented by setting the corresponding bit in the
bit field.
Program Flow, Event: Event
Exception event
1 17:16
15:14
13:5
4:0
11 – The item contains an event
11 – Exception event:
Reserved
Exception cause, according to “ESR Exception Cause”,
defined in
Table 2-11, and:
01001 – Debug exception: Breakpoint, Stop
01010 – Interrupt
01011 – Non-maskable break
01100 – Break
Event: Event Time Stamp 1 17:16
15:14
13:0
11 – The item contains an event
01 – Time stamp
Cycle count since last time stamp
Program Flow with Cycle Count:
Branches and short cycle count
1 17:16
15:14
13:8
7
6:1
0
00 - The item contains program flow branches
01, 10 - Number of branches (N) counted (1 - 2)
Cycle count for previously executed instructions
Branch is taken if set to one, otherwise it is not taken
Cycle count for previously executed instructions
Branch is taken if set to one, otherwise it is not taken
Program Flow with Cycle Count:
Branch and long cycle count
1 17:16
15:14
13:1
0
00 - The item contains program flow branches
11 - The item contains branch and long cycle count
Cycle count for previously executed instructions
Branch is taken if set to one, otherwise it is not taken
Table 2-54: Trace Counter Data Entities (Cont’d)
Entity Item Bits Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module