Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 111
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Non-Intrusive Profiling
With extended debugging, non-intrusive profiling is provided, which uses a Profiling Buffer
to store program execution statistics. The size of the profiling buffer can be configured
from 4KB to 128KB using the parameter
C_DEBUG_PROFILE_SIZE. By setting
C_DEBUG_PROFILE_SIZE to 0 (None), non-intrusive profiling is disabled.
The Profiling Buffer is divided into a number of bins, each counting the number of executed
instructions or clock cycles within a certain address range. Each bin counts up to 2
36
- 1 =
68719476735 instructions or cycles.
The address range of each bin is determined by the buffer size and the profiled address
range defined using the Profiling Low Address Register and Profiling High Address Register.
Profiling can be started or stopped using the Profiling Control Register or by cross trigger
events (see
Table 2-62).
The debug registers used to configure and control profiling, and to read or write the
Profiling Buffer, are listed in
Table 2-55.
The DBG_CTRL value indicates the value to use in the MDM Debug Register Access Control
Register to access the register, used with MDM software access to debug registers.
Table 2-55: MicroBlaze Profiling Debug Registers
Register Name Size (bits)
MDM
Command
DBG_CTRL
Value
R/W Description
Profiling Control 8 0111 0001 4E207 W
Enable or disable profiling, configure
counting method and bin usage
Profiling Low
Address
30
0111 0010 4E41D W
Defines the low address of the
profiled address range
Profiling High
Address
30
0111 0011 4E61D W
Defines the high address of the
profiled address range
Profiling Buffer
Address
9 - 14 0111 0100
9: 4E808
10: 4E809
...
14: 4E80D
W
Sets the address (bin) in the Profiling
Buffer to read or write
Profiling Data
Read
36 0111 0110 4EC23 R Read data from the Profiling Buffer
Profiling Data
Write
32 0111 0111 4EE1F W Write data to the Profiling Buffer
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module