Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 107
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Trace Control Register
The Trace Control Register (TCTRLR) is used to define the trace behavior. This register is a
write-only register. Issuing a read request has no effect, and undefined data is read. See the
following figure and table.
Trace Command Register
The Trace Command Register (TCMDR) is used to issue commands to clear, start, or stop
trace, as well as sample the number of trace items. This register is a write-only register.
Issuing a read request has no effect, and undefined data is read. See the following figure
and table.
X-Ref Target - Figure 2-31
Figure 2-31: Trace Control Register
04
Reserved
31 321
SR
SLSPCFH
22 521 6
Tracepoint
Level
X19767-082517
Table 2-50: Trace Control Register (TCTRLR)
Bits Name Description Reset Value
21:6 Tracepoint
Change corresponding breakpoint or watchpoint to a tracepoint
0
5:4 Level
Trace compression level:
00 = Complete trace, not available with C_DEBUG_EXTERNAL_TRACE
01 = Program flow
10 = Event
11 = Program flow and cycle count
00
3Full Halt
Debug Halt on full trace buffer or cycle count overflow
0
2Save PC
Level 01 and 11: Save new program counter for all taken branches
Level 10: Save new program counter for all function calls
0
1Save Load
Save load and get instruction new data value
0
0Save Return
Save new program counter for return instructions
0
X-Ref Target - Figure 2-32
Figure 2-32: Trace Command Register
04
Reserved
31 321
SAM
STOP
STACLR
X19768-091117
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module