Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 15
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
TNCAPUTD Ra,Rb 010011 00000 Ra Rb 0N1TA0
00000
FSL Rb[28:31] := Ra (control write)
MSR[C] := FSL_M_Full if N = 1
FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, float
1
FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, float
1
FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, float
1
FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, float
1
FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000 Rd := 1 if (Rb = NaN or Ra = NaN,
float
1
) else
Rd := 0
FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000 Rd := 1 if (Rb < Ra, float
1
) else
Rd := 0
FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000 Rd := 1 if (Rb = Ra, float
1
) else
Rd := 0
FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000 Rd := 1 if (Rb <= Ra, float
1
) else
Rd := 0
FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000 Rd := 1 if (Rb > Ra, float
1
) else
Rd := 0
FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000 Rd := 1 if (Rb != Ra, float
1
) else
Rd := 0
FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000 Rd := 1 if (Rb >= Ra, float
1
) else
Rd := 0
FLT Rd,Ra 010110 Rd Ra 0 01010000000 Rd := float (Ra)
1
FINT Rd,Ra 010110 Rd Ra 0 01100000000 Rd := int (Ra)
1
FSQRT Rd,Ra 010110 Rd Ra 0 01110000000 Rd := sqrt (Ra)
1
MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm)
BSRLI Rd,Ra,Imm 011001 Rd Ra 00000000000 &
Imm5
Rd : = 0 & (Ra >> Imm5)
BSRAI Rd,Ra,Imm 011001 Rd Ra 00000010000 &
Imm5
Rd := s(Ra >> Imm5)
BSLLI Rd,Ra,Imm 011001 Rd Ra 00000100000 &
Imm5
Rd := (Ra << Imm5) & 0
BSEFI Rd,Ra,
Imm
W
,Imm
S
011001 Rd Ra 01000 &
Imm
W
& 0 & Imm
S
Rd[0:31-Imm
W
] := 0
Rd[32-Imm
W
:31] := (Ra >> Imm
S
)
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module