Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 16
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
BSIFI Rd,Ra,
Width,Imm
S
011001 Rd Ra 10000 &
Imm
W
& 0 & Imm
S
M := (0xffffffff << (Imm
W
+ 1)) xor
(0xffffffff << Imm
S
)
Rd := ((Ra << Imm
S
) and M) xor
(Rd and M)
Imm
W
:= Imm
S
+ Width - 1
TNEAGET Rd,FSLx 011011 Rd 00000 0N0TAE000000 &
FSLx
Rd := FSLx (data read, blocking if
N = 0)
MSR[FSL] := 1 if (FSLx_S_Control = 1)
MSR[C] := not FSLx_S_Exists if N = 1
TNAPUT Ra,FSLx 011011 00000 Ra 1N0TA0000000 &
FSLx
FSLx := Ra (data write, block if N = 0)
MSR[C] := FSLx_M_Full if N = 1
TNECAGET Rd,FSLx 011011 Rd 00000 0N1TAE000000 &
FSLx
Rd := FSLx (control read, block if N =
0)
MSR[FSL] := 1 if (FSLx_S_Control = 0)
MSR[C] := not FSLx_S_Exists if N = 1
TNCAPUT Ra,FSLx 011011 00000 Ra 1N1TA0000000 &
FSLx
FSLx := Ra (control write, block if N =
0)
MSR[C] := FSLx_M_Full if N = 1
OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb
PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else
Rd := 2 if (Rb[8:15] = Ra[8:15]) else
Rd := 3 if (Rb[16:23] = Ra[16:23]) else
Rd := 4 if (Rb[24:31] = Ra[24:31]) else
Rd := 0
AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb
XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb
PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rb = Ra) else
Rd := 0
ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and Rb
PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rb != Ra) else
Rd := 0
SRA Rd,Ra 100100 Rd Ra 0000000000000001 Rd := s(Ra >> 1)
C := Ra[31]
SRC Rd,Ra 100100 Rd Ra 0000000000100001 Rd := C & (Ra >> 1)
C := Ra[31]
SRL Rd,Ra 100100 Rd Ra 0000000001000001 Rd := 0 & (Ra >> 1)
C := Ra[31]
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module