Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 17
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31])
SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31])
CLZ Rd, Ra 100100 Rd Ra 0000000011100000 Rd = clz(Ra)
SWAPB Rd, Ra 100100 Rd Ra 0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]
SWAPH Rd, Ra 100100 Rd Ra 0000000111100010 Rd = (Ra)[16:31, 0:15]
WIC Ra,Rb 100100 00000 Ra Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if
(
C_ICACHE_LINE_LEN = 4)
ICache_Line[Ra >> 5].Tag := 0 if
(
C_ICACHE_LINE_LEN = 8)
ICache_Line[Ra >> 6].Tag := 0 if
(
C_ICACHE_LINE_LEN = 16)
WDC Ra,Rb 100100 00000 Ra Rb 00001100100 Cache line is cleared, discarding
stored data.
DCache_Line[Ra >> 4].Tag := 0 if
(
C_DCACHE_LINE_LEN = 4)
DCache_Line[Ra >> 5].Tag := 0 if
(
C_DCACHE_LINE_LEN = 8)
DCache_Line[Ra >> 6].Tag := 0 if
(
C_DCACHE_LINE_LEN = 16)
WDC.FLUSH Ra,Rb 100100 00000 Ra Rb 00001110100 Cache line is flushed, writing stored
data to memory, and then cleared.
Used when
C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR Ra,Rb 100100 00000 Ra Rb 00001100110 Cache line with matching address is
cleared, discarding stored data. Used
when
C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR.EA
Ra,Rb
100100 00000 Ra Rb 00011100110 Cache line with matching extended
address Ra & Rb is cleared. Used
when
C_DCACHE_USE_WRITEBACK = 1.
MTS Sd,Ra 100101 00000 Ra 11 & Sd SPR[Sd] := Ra, where:
· SPR[0x0001] is MSR
· SPR[0x0007] is FSR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO[LSH]
· SPR[0x1004] is TLBHI
· SPR[0x1005] is TLBSX
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module