Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 151
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_DC
M_ACE_DC
C_M_AXI_DC_DATA_WIDTH 32: Default, single word accesses and burst accesses
with C_DCACHE_LINE_LEN word busts used with AXI4
and ACE.
Write bursts are only used with AXI4 when
C_DCACHE_USE_WRITEBACK is set to 1.
128: Used when C_DCACHE_DATA_WIDTH is set to 1
and C_DCACHE_LINE_LEN is set to 4 with AXI4. Only
single accesses can occur.
256: Used when C_DCACHE_DATA_WIDTH is set to 1
and C_DCACHE_LINE_LEN is set to 8 with AXI4. Only
single accesses can occur.
512: Used when C_DCACHE_DATA_WIDTH is set to 2, or
when it is set to 1 and C_DCACHE_LINE_LEN is set to
16 with AXI4. Only single accesses can occur.
M_AXI_IC
M_ACE_IC
NUM_READ_OUTSTANDING 1: Default for 128-bit, 256-bit and 512-bit masters, a
single outstanding read.
2: Default for 32-bit masters, 2 simultaneous
outstanding reads.
8: Used for 32-bit masters when C_ICACHE_STREAMS is
set to 1, allowing 8 simultaneous outstanding reads.
Can be set to 1, 2, or 8.
M_AXI_DC
M_ACE_DC
NUM_READ_OUTSTANDING 1: Default for 128-bit, 256-bit and 512-bit masters, a
single outstanding read.
2: Default for 32-bit masters, 2 simultaneous
outstanding reads.
Can be set to 1 or 2.
M_AXI_DC
M_ACE_DC
NUM_WRITE_OUTSTANDING 32: Default, 32 simultaneous outstanding writes.
Can be set to 1, 2, 4, 8, 16, or 32.
Table 3-5: AXI Memory Mapped Interface Parameters (Cont’d)
Interface Parameter Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module