Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 153
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
The instruction cache interface (M_AXI_IC) address width can range from 32 - 64 bits when
the MMU physical address extension (PAE) is enabled, depending on the value of the
parameter
C_ADDR_SIZE.
The data cache interface (M_AXI_DC or M_ACE_DC) address width can range from 32 - 64 bits,
depending on the value of the parameter C_ADDR_SIZE.
See the AMBA AXI and ACE Protocol Specification (Arm IHI 0022E) [Ref 15] document for
details.
Stream Interfaces
The MicroBlaze AXI4-Stream interfaces (M0_AXIS..M15_AXIS, S0_AXIS..S15_AXIS) are
implemented as 32-bit masters and slaves. See the AMBA 4 AXI4-Stream Protocol
Specification, Version 1.0 (
Arm IHI 0051A) [Ref 14] document for further details.
Write Operation
A write to the stream interface is performed by MicroBlaze using one of the put or putd
instructions. A write operation transfers the register contents to an output AXI4 interface.
The transfer is completed in a single clock cycle for blocking mode writes (put and cput
instructions) as long as the interface is not busy. If the interface is busy, the processor stalls
until it becomes available. The non-blocking instructions (with prefix n), always complete in
a single clock cycle even if the interface is busy. If the interface was busy, the write is
inhibited and the carry bit is set in the MSR.
The control instructions (with prefix c) set the AXI4-Stream TLAST output, to ‘1’, which is
used to indicate the boundary of a packet.
M_AXI_DC
M_ACE_DC
C_M_AXI_DC_AWCACHE Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, exclusive access:
• Normal Non-cacheable Non-bufferable (0010)
C_M_AXI_DC_ARPROT
C_M_AXI_DC_AWPROT
Access Permission:
• Unprivileged, secure data access (000) if input signal
Non_Secure[2] = 0
• Unprivileged, non-secure data access (010) if input signal
Non_Secure[2] = 1
C_M_AXI_DC_ARQOS Quality of Service, read access:
• Priority 12 ((1100)
C_M_AXI_DC_AWQOS Quality of Service, write access:
• Priority 8 (1000)
Table 3-6: AXI Interface Signal Definitions (Cont’d)
Interface Signal Description
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module