Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 154
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Read Operation
A read from the stream interface is performed by MicroBlaze using one of the get or getd
instructions. A read operations transfers the contents of an input AXI4 interface to a general
purpose register. The transfer is typically completed in 2 clock cycles for blocking mode
reads as long as data is available. If data is not available, the processor stalls at this
instruction until it becomes available. In the non-blocking mode (instructions with prefix n),
the transfer is completed in one or two clock cycles irrespective of whether or not data was
available. In case data was not available, the transfer of data does not take place and the
carry bit is set in the MSR.
The data get instructions (without prefix c) expect the AXI4-Stream TLAST input to be
cleared to ‘0’, otherwise the instructions will set MSR[FSL] to ‘1’. Conversely, the control get
instructions (with prefix c) expect the
TLAST input to be set to ‘1’, otherwise the instructions
will set MSR[FSL] to ‘1’. This can be used to check for the boundary of a packet.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module