Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 158
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
LMB Transactions
The following diagrams provide examples of LMB bus operations.
Generic Write Operations
X-Ref Target - Figure 3-4
Figure 3-4: LMB Generic Write Operation, 0 Wait States
A0
BE0
D0
Don’t Care
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Wirte_Strobe
Data_Read
Ready
Wait
CE
UE
X19788-091217
X-Ref Target - Figure 3-5
Figure 3-5: LMB Generic Write Operation, N Wait State
A0
BE0
D0
Don’t Care
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Wirte_Strobe
Data_Read
Ready
Wait
CE
UE
X19789-091217
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module