Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 168
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_DC_ARVALID 2856 std_logic
M_AXI_DC_ARUSER 2857 to 2861 std_logic_vector
M_AXI_DC_ARDOMAIN
1
2862 to 2863 std_logic_vector
M_AXI_DC_ARSNOOP
1
2864 to 2867 std_logic_vector
M_AXI_DC_ARBAR
1
2868 to 2869 std_logic_vector
M_AXI_DC_RREADY 2870 std_logic
M_AXI_DC_RACK
1
2871 std_logic
M_AXI_DC_ACREADY
1
2872 std_logic
M_AXI_DC_CRVALID
1
2873 std_logic
M_AXI_DC_CRRESP
1
2874 to 2878 std_logic_vector
M_AXI_DC_CDVALID
1
2879 std_logic
M_AXI_DC_CDLAST
1
2880 std_logic
Trace_Instruction 2881 to 2912 std_logic_vector
Trace_Valid_Instr 2913 std_logic
Trace_PC 2914 to 2945 std_logic_vector
Trace_Reg_Write 2978 std_logic
Trace_Reg_Addr 2979 to 2983 std_logic_vector
Trace_MSR_Reg 2984 to 2998 std_logic_vector
Trace_PID_Reg 2999 to 3006 std_logic_vector
Trace_New_Reg_Value 3007 to 3038 std_logic_vector
Trace_Exception_Taken 3071 std_logic
Trace_Exception_Kind 3072 to 3076 std_logic_vector
Trace_Jump_Taken 3077 std_logic
Trace_Delay_Slot 3078 std_logic
Trace_Data_Address 3079 to 3142 std_logic_vector
Trace_Data_Write_Value 3143 to 3174 std_logic_vector
Trace_Data_Byte_Enable 3207 to 3210 std_logic_vector
Trace_Data_Access 3215 std_logic
Trace_Data_Read 3216 std_logic
Trace_Data_Write 3217 std_logic
Trace_DCache_Req 3218 std_logic
Trace_DCache_Hit 3219 std_logic
Trace_DCache_Rdy 3220 std_logic
Trace_DCache_Read 3221 std_logic
Trace_ICache_Req 3222 std_logic
Trace_ICache_Hit 3223 std_logic
Trace_ICache_Rdy 3224 std_logic
Trace_OF_PipeRun 3225 std_logic
Trace_EX_PipeRun 3226 std_logic
Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d)
Signal Name Bus Index Range VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module