Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 21
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
LWEA Rd,Ra,Rb 110010 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd := *Addr
SB Rd,Ra,Rb
SBR Rd,Ra,Rb
110100 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr[0:8] := Rd[24:31]
SBEA Rd,Ra,Rb 110100 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr[0:8] := Rd[24:31]
SH Rd,Ra,Rb
SHR Rd,Ra,Rb
110101 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr[0:16] := Rd[16:31]
SHEA Rd,Ra,Rb 110101 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr[0:16] := Rd[16:31]
SW Rd,Ra,Rb
SWR Rd,Ra,Rb
110110 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr := Rd
SWX Rd,Ra,Rb 110110 Rd Ra Rb 10000000000 Addr := Ra + Rb
*Addr := Rd if Reservation = 1
Reservation := 0
SWEA Rd,Ra,Rb 110110 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr := Rd
LBUI Rd,Ra,Imm 111000 Rd Ra Imm Addr := Ra + s(Imm)
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LHUI Rd,Ra,Imm 111001 Rd Ra Imm Addr := Ra + s(Imm)
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LWI Rd,Ra,Imm 111010 Rd Ra Imm Addr := Ra + s(Imm)
Rd := *Addr
SBI Rd,Ra,Imm 111100 Rd Ra Imm Addr := Ra + s(Imm)
*Addr[0:7] := Rd[24:31]
SHI Rd,Ra,Imm 111101 Rd Ra Imm Addr := Ra + s(Imm)
*Addr[0:15] := Rd[16:31]
SWI Rd,Ra,Imm 111110 Rd Ra Imm Addr := Ra + s(Imm)
*Addr := Rd
1. Due to the many different corner cases involved in floating-point arithmetic, only the normal behavior is described. A full
description of the behavior can be found in Chapter 5, “MicroBlaze Instruction Set Architecture.”
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module