Xilinx MicroBlaze - Page 20

MicroBlaze Processor Reference Guide 20
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
BRAID Imm 101110 00000 11000 Imm PC := s(Imm)
BRALID Rd,Imm 101110 Rd 11100 Imm PC := s(Imm)
Rd := PC
BRKI Rd,Imm 101110 Rd 01100 Imm PC := s(Imm)
Rd := PC
MSR[BIP] := 1
BEQI Ra,Imm 101111 00000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEI Ra,Imm 101111 00001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTI Ra,Imm 101111 00010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEI Ra,Imm 101111 00011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTI Ra,Imm 101111 00100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEI Ra,Imm 101111 00101 Ra Imm PC := PC + s(Imm) if Ra >= 0
BEQID Ra,Imm 101111 10000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEID Ra,Imm 101111 10001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTID Ra,Imm 101111 10010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEID Ra,Imm 101111 10011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTID Ra,Imm 101111 10100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEID Ra,Imm 101111 10101 Ra Imm PC := PC + s(Imm) if Ra >= 0
LBU Rd,Ra,Rb
LBUR Rd,Ra,Rb
110000 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LBUEA Rd,Ra,Rb 110000 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LHU Rd,Ra,Rb
LHUR Rd,Ra,Rb
110001 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LHUEA Rd,Ra,Rb 110001 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LW Rd,Ra,Rb
LWR Rd,Ra,Rb
110010 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd := *Addr
LWX Rd,Ra,Rb 110010 Rd Ra Rb 10000000000 Addr := Ra + Rb
Rd := *Addr
Reservation := 1
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31
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