MicroBlaze Processor Reference Guide 215
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
br
Unconditional Branch
br
rB
Branch
bra
rB
Branch Absolute
brd
rB
Branch with Delay
brad
rB
Branch Absolute with Delay
brld
rD, rB
Branch and Link with Delay
brald
rD, rB
Branch Absolute and Link with Delay
1 0 0 1 1 0 rD D A L 0 0 rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Branch to the instruction located at address determined by rB.
The mnemonics brld and brald will set the L bit. If the L bit is set, linking will be performed. The
current value of PC will be stored in rD.
The mnemonics bra, brad and brald will set the A bit. If the A bit is set, it means that the branch is to
an absolute value and the target is the value in rB, otherwise, it is a relative branch and the target will
be PC + rB.
The mnemonics brd, brad, brld and brald will set the D bit. The D bit determines whether there is a
branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following the branch (that is, in the branch delay slot) is allowed to complete execution before
executing the target instruction.
If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the
branch is the target instruction.
Pseudocode
if L = 1 then
(rD) ← PC
if A = 1 then
PC
← (rB)
else
PC ← PC + (rB)
if D = 1 then
allow following instruction to complete execution
Registers Altered
•rD
•PC
Latency
• 2 cycles (if the D bit is set)
• 3 cycles (if the D bit is not set)
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