MicroBlaze Processor Reference Guide 218
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
Registers Altered
•rD
•PC
• MSR[UM], MSR[VM]
Latency
• 1 cycle (if successful branch prediction occurs)
• 2 cycles (if the D bit is set)
• 3 cycles (if the D bit is not set, or a branch prediction mispredict occurs with
C_AREA_OPTIMIZED=0)
• 7-9 cycles (if a branch prediction mispredict occurs with
C_AREA_OPTIMIZED=2)
Notes
The instructions brli and brali are not available.
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
“imm” for details on using 32-bit immediate values.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
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