MicroBlaze Processor Reference Guide 224
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
Pseudocode
if E = 1 then
(rD)[0:31-IMM
W
] ← 0
(rD)[32-IMM
W
:31] ← (rA) >> IMM
S
else if I = 1 then
mask ← (0xffffffff << (IMM
W
+ 1)) ⊕ (0xffffffff << IMM
S
)
(rD)
← ((rA) << IMM
S
) ∧ mask) ∨ ((rD) ∧ mask)
else if S = 1 then
(rD) ← (rA) << IMM
else if T = 1 then
if IMM
≠ 0 then
(rD)[0:IMM-1] ← (rA)[0]
(rD)[IMM:31]
← (rA) >> IMM
else
(rD) ← (rA)
else
(rD)
← (rA) >> IMM
Registers Altered
•rD
Latency
• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with
C_AREA_OPTIMIZED=1
Notes
These are not Type B Instructions. There is no effect from a preceding imm instruction.
These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift
instructions (C_USE_BARREL=1).
The assembler code “bsifi rD, rA, width, shift” denotes the actual bit field width, not the IMM
W
field,
which is computed by IMM
W
= shift + width - 1.
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