Xilinx MicroBlaze - Page 226

MicroBlaze Processor Reference Guide 227
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
fadd
Floating-Point Arithmetic Add
fadd
rD, rA, rB
Add
0 1 0 1 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
The floating-point sum of registers rA and rB, is placed into register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
(rD)
← 0xFFC00000
FSR[DO] ← 1
ESR[EC] ← 00110
else if isSigNaN(rA) or isSigNaN(rB)or
(isPosInfinite(rA) and isNegInfinite(rB)) or
(isNegInfinite(rA) and isPosInfinite(rB))) then
(rD)
← 0xFFC00000
FSR[IO] ← 1
ESR[EC] ← 00110
else if isQuietNaN(rA) or isQuietNaN(rB) then
(rD)
← 0xFFC00000
else if isDnz((rA)+(rB)) then
(rD)
← signZero((rA)+(rB))
FSR[UF] ← 1
ESR[EC] ← 00110
else if isNaN((rA)+(rB)) then
(rD)
← signInfinite((rA)+(rB))
FSR[OF] ← 1
ESR[EC]
← 00110
else
(rD) ← (rA) + (rB)
Registers Altered
• rD, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
•FSR[IO,UF,OF,DO]
Latency
• 4 cycles with C_AREA_OPTIMIZED=0
• 6 cycles with
C_AREA_OPTIMIZED=1
• 1 cycle with
C_AREA_OPTIMIZED=2
Note
This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.
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