Xilinx MicroBlaze

MicroBlaze Processor Reference Guide 230
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
fdiv
Floating-Point Arithmetic Division
fdiv
rD, rA, rB
Divide
0 1 0 1 1 0 rD rA rB 0 0 1 1 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
The floating-point value in rB is divided by the floating-point value in rA and the result is placed into
register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
(rD) ← 0xFFC00000
FSR[DO] ← 1
ESR[EC]
← 00110
else
if isSigNaN(rA) or isSigNaN(rB) or (isZero(rA) and isZero(rB)) or
(isInfinite(rA) and isInfinite(rB)) then
(rD)
← 0xFFC00000
FSR[IO] ← 1
ESR[EC] ← 00110
else if isQuietNaN(rA) or isQuietNaN(rB) then
(rD) ← 0xFFC00000
else if isZero(rA) and not isInfinite(rB) then
(rD)
← signInfinite((rB)/(rA))
FSR[DZ] ← 1
ESR[EC]
← 00110
else if isDnz((rB) / (rA)) then
(rD) ← signZero((rB) / (rA))
FSR[UF]
← 1
ESR[EC] ← 00110
else if isNaN((rB)/(rA)) then
(rD)
← signInfinite((rB) / (rA))
FSR[OF] ← 1
ESR[EC] ← 00110
else
(rD)
← (rB) / (rA)
Registers Altered
• rD, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
• FSR[IO,UF,OF,DO,DZ]
Latency
• 28 cycles with C_AREA_OPTIMIZED=0
• 30 cycles with
C_AREA_OPTIMIZED=1
• 24 cycles with
C_AREA_OPTIMIZED=2
Note
This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.
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