Xilinx MicroBlaze - Page 234

MicroBlaze Processor Reference Guide 235
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
fsqrt
Floating-Point Arithmetic Square Root
fsqrt
rD, rA
Square Root
0 1 0 1 1 0 rD rA 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Performs a floating-point square root on the value in rA and puts the result in register rD.
Pseudocode
if isDnz(rA) then
(rD)
← 0xFFC00000
FSR[DO] ← 1
ESR[EC] ← 00110
else if isSigNaN(rA) then
(rD)
← 0xFFC00000
FSR[IO] ← 1
ESR[EC]
← 00110
else if isQuietNaN(rA) then
(rD) ← 0xFFC00000
else if (rA) < 0 then
(rD)
← 0xFFC00000
FSR[IO] ← 1
ESR[EC]
← 00110
else if (rA) = -0 then
(rD) ← -0
else
(rD)
← sqrt ((rA))
Registers Altered
• rD, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
•FSR[IO,DO]
Latency
• 27 cycles with C_AREA_OPTIMIZED=0
• 29 cycles with
C_AREA_OPTIMIZED=1
• 23 cycles with
C_AREA_OPTIMIZED=2
Note
This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended).
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