MicroBlaze Processor Reference Guide 266
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
ori
Logical OR with Immediate
ori
rD, rA, IMM
1 0 1 0 0 0 rD rA IMM
0 6 11 16
31
Description
The contents of register rA are ORed with the extended IMM field, sign-extended to 32 bits; the result
is placed into register rD.
Pseudocode
(rD) ← (rA) ∨ sext(IMM)
Registers Altered
•rD
Latency
• 1 cycle
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
“imm” for details on using 32-bit immediate values.
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