MicroBlaze Processor Reference Guide 279
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
rtsd
Return from Subroutine
rtsd
rA, IMM
1 0 1 1 0 1 1 0 0 0 0 rA IMM
0 6 11 16
31
Description
Return from subroutine will branch to the location specified by the contents of rA plus the IMM field,
sign-extended to 32 bits.
This instruction always has a delay slot. The instruction following the RTSD is always executed before
the branch target.
Pseudocode
PC ← (rA) + sext(IMM)
allow following instruction to complete execution
Registers Altered
•PC
Latency
• 1 cycle (if successful branch prediction occurs)
• 2 cycles (with Branch Target Cache disabled)
• 3 cycles (if branch prediction mispredict occurs with
C_AREA_OPTIMIZED=0)
• 7-9 cycles (if a branch prediction mispredict occurs with
C_AREA_OPTIMIZED=2)
Notes
Convention is to use general purpose register r15 as rA.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
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