Xilinx MicroBlaze - Page 279

MicroBlaze Processor Reference Guide 280
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
sb
Store Byte
sb
rD, rA, rB
sbr
rD, rA, rB
sbea
rD, rA, rB
1 1 0 1 0 0 rD rA rB 0 R 0 EA 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Stores the contents of the least significant byte of register rD, into the memory location that results
from adding the contents of registers rA and rB.
If the R bit is set, a byte reversed memory location is used, storing data with the opposite endianness
of the endianness defined by the E bit (if virtual protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled,
and the instruction is not explicitly allowed.
Pseudocode
if EA = 1 then
Addr
← (rA) & (rB)
else
Addr ← (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
← 10010;ESR[S]← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
← 10000;ESR[S]← 1; ESR[DIZ] ← No-access-allowed
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else
Mem(Addr)
← (rD)[24:31]
Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
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