Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 32
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Branch Target Register (BTR)
The Branch Target Register only exists if the MicroBlaze processor is configured to use
exceptions. The register stores the branch target address for all delay slot branch
instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a
delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address
stored in BTR instead of the normal exception return address stored in R17. When read with
the MFS instruction, the BTR is specified by setting Sa = 0x000B. The BTR register is
illustrated in the following figure and
Table 2-13 provides bit descriptions and reset values.
Floating-
point unit
20:26 Reserved 0
Privileged
instruction
20:26 Reserved 0
Stack
protection
violation
20:26 Reserved 0
Stream 20:22 Reserved 0
23:26 FSL AXI4-Stream index that caused the exception 0
Data
storage
20 DIZ Data storage - Zone protection
0 = Did not occur
1 = Occurred
0
21 S Data storage - Store instruction
0 = Did not occur
1 = Occurred
0
22:26 Reserved 0
Instruction
storage
20 DIZ Instruction storage - Zone protection
0 = Did not occur
1 = Occurred
0
21:26 Reserved 0
Data TLB
miss
20 Reserved 0
21 S Data TLB miss - Store instruction
0 = Did not occur
1 = Occurred
0
22:26 Reserved 0
Instruction
TLB miss
20:26 Reserved 0
Table 2-12: Exception Specific Status (ESS) (Cont’d)
Exception
Cause
Bits Name Description Reset Value
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module