Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 44
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Table 2-26: Processor Version Register 2 (PVR2)
Bits Name Description Value
0 DAXI Data side AXI4 or ACE in use C_D_AXI
1 DLMB Data side LMB in use C_D_LMB
2 IAXI Instruction side AXI4 or ACE in use C_I_AXI
3 ILMB Instruction side LMB in use C_I_LMB
4 IRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE
5 IRQPOS Interrupt edge is positive C_EDGE_IS_POSITIVE
6 CEEXC Generate bus exceptions for ECC
correctable errors in LMB memory
C_ECC_USE_CE_EXCEPTION
7 FREQ Select implementation to optimize
processor frequency
C_AREA_OPTIMIZED=2
(Frequency)
8 Reserved 0
9 Reserved 1
10 ACE Use ACE interconnect C_INTERCONNECT = 3 (ACE)
11 AXI4DP Data Peripheral AXI interface uses AXI4
protocol, with support for exclusive access
C_M_AXI_DP_EXCLUSIVE_
ACCESS
12 FSL Use extended AXI4-Stream instructions C_USE_EXTENDED_FSL_INSTR
13 FSLEXC Generate exception for AXI4-Stream
control bit mismatch
C_FSL_EXCEPTION
14 MSR Use msrset and msrclr instructions C_USE_MSR_INSTR
15 PCMP Use pattern compare and CLZ instructions C_USE_PCMP_INSTR
16 AREA Select implementation to optimize area
with lower instruction throughput
C_AREA_OPTIMIZED = 1 (Area)
17 BS Use barrel shifter C_USE_BARREL
18 DIV Use divider C_USE_DIV
19 MUL Use hardware multiplier C_USE_HW_MUL > 0 (None)
20 FPU Use FPU C_USE_FPU > 0 (None)
21 MUL64 Use 64-bit hardware multiplier C_USE_HW_MUL = 2 (Mul64)
22 FPU2 Use floating-point conversion and square
root instructions
C_USE_FPU = 2 (Extended)
23 IMPEXC Allow imprecise exceptions for ECC errors
in LMB memory
C_IMPRECISE_EXCEPTIONS
24 Reserved 0
25 OP0EXC Generate exception for 0x0 illegal opcode C_OPCODE_0x0_ILLEGAL
26 UNEXC Generate exception for unaligned data
access
C_UNALIGNED_EXCEPTIONS
27 OPEXC Generate exception for any illegal opcode C_ILL_OPCODE_EXCEPTION
28 AXIDEXC Generate exception for M_AXI_D error C_M_AXI_D_BUS_EXCEPTION
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module