Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 45
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
29 AXIIEXC Generate exception for M_AXI_I error C_M_AXI_I_BUS_EXCEPTION
30 DIVEXC Generate exception for division by zero or
division overflow
C_DIV_ZERO_EXCEPTION
31 FPUEXC Generate exceptions from FPU C_FPU_EXCEPTION
Table 2-27: Processor Version Register 3 (PVR3)
Bits Name Description Value
0 DEBUG Use debug logic C_DEBUG_ENABLED > 0
1 EXT_DEBUG Use extended debug logic C_DEBUG_ENABLED = 2
(Extended)
2 Reserved
3:6 PCBRK Number of PC breakpoints C_NUMBER_OF_PC_BRK
7:9 Reserved
10:12 RDADDR Number of read address breakpoints C_NUMBER_OF_RD_ADDR_BRK
13:15 Reserved
16:18 WRADDR Number of write address breakpoints C_NUMBER_OF_WR_ADDR_BRK
19 Reserved 0
20:24 FSL Number of AXI4-Stream links C_FSL_LINKS
25:28 Reserved
29:31 BTC_SIZE Branch Target Cache size C_BRANCH_TARGET_CACHE_SIZE
Table 2-26: Processor Version Register 2 (PVR2) (Cont’d)
Bits Name Description Value
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module