Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 8
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Features
The MicroBlaze soft core processor is highly configurable, allowing you to select a specific
set of features required by your design.
The fixed feature set of the processor includes:
• Thirty-two 32-bit general purpose registers
• 32-bit instruction word with three operands and two addressing modes
• Default 32-bit address bus, extensible to 64 bits
• Single issue pipeline
In addition to these fixed features, the MicroBlaze processor is parameterized to allow
selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze
support a subset of the optional features described in this manual. Only the latest
(preferred) version of MicroBlaze (v10.0) supports all options.
RECOMMENDED: Xilinx recommends that all new designs use the latest preferred version of the
MicroBlaze processor.
The following table provides an overview of the configurable features by MicroBlaze
versions.
Table 2-1: Configurable Feature Overview by MicroBlaze Version
Feature
MicroBlaze versions
v9.2 v9.3 v9.4 v9.5 v9.6 v10.0
Version Status
deprecated deprecated deprecated deprecated deprecated preferred
Processor pipeline depth
3/5 3/5 3/5 3/5 3/5 3/5/8
Local Memory Bus (LMB) data side
interface
option option option option option option
Local Memory Bus (LMB)
instruction side interface
option option option option option option
Hardware barrel shifter
option option option option option option
Hardware divider
option option option option option option
Hardware debug logic
option option option option option option
Stream link interfaces
0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI 0-16 AXI
Machine status set and clear
instructions
option option option option option option
Cache line word length
4, 8 4, 8 4, 8 4, 8, 16 4, 8, 16 4, 8, 16
Hardware exception support
option option option option option option
Pattern compare instructions
option option option option option option
Floating-point unit (FPU)
option option option option option option
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module