Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 9
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Disable hardware multiplier
1
option option option option option option
Hardware debug readable ESR and
EAR
Yes Yes Yes Yes Yes Yes
Processor Version Register (PVR)
option option option option option option
Area or speed optimized
option option option option option option
Hardware multiplier 64-bit result
option option option option option option
LUT cache memory
option option option option option option
Floating-point conversion and
square root instructions
option option option option option option
Memory Management Unit (MMU)
option option option option option option
Extended stream instructions
option option option option option option
Use Cache Interface for All I-Cache
Memory Accesses
option option option option option option
Use Cache Interface for All D-Cache
Memory Accesses
option option option option option option
Use Write-back Caching Policy for
D-Cache
option option option option option option
Branch Target Cache (BTC)
option option option option option option
Streams for I-Cache
option option option option option option
Victim handling for I-Cache
option option option option option option
Victim handling for D-Cache
option option option option option option
AXI4 (M_AXI_DP) data side interface
option option option option option option
AXI4 (M_AXI_IP) instruction side
interface
option option option option option option
AXI4 (M_AXI_DC) protocol for D-
Cache
option option option option option option
AXI4 (M_AXI_IC) protocol for I-
Cache
option option option option option option
AXI4 protocol for stream accesses
option option option option option option
Fault tolerant features
option option option option option option
Force distributed RAM for cache
tags
option option option option option option
Configurable cache data widths
option option option option option option
Count Leading Zeros instruction
option option option option option option
Memory Barrier instruction
Yes Yes Yes Yes Yes Yes
Stack overflow and underflow
detection
option option option option option option
Allow stream instructions in user
mode
option option option option option option
Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont’d)
Feature
MicroBlaze versions
v9.2 v9.3 v9.4 v9.5 v9.6 v10.0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module