Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 19
PG232 July 02, 2019 www.xilinx.com
Chapter 2: Product Specification
emb_nonimg_tuser[95:0] Output
95-80 CRC
(3)
79-72 ECC
71-70 Reserved
69-64 Data Type
63-48 Word Count
47-32 Line Number
31-16 Frame Number
15-2 Reserved
1 Packet Error
0 Start of frame
(2)
emb_nonimg_tvalid Output Data valid
AXI4-Stream Interface when Video Format Bridge is Not Present
video_out_tdata[n-1:0] Output
Data
n is based on TDATA width selected in the Vivado IDE.
video_out_tdest[n-1:0] Output
n is based on TDEST width selected in the Vivado IDE:
9-4 Data type
3-0 Virtual Channel Identifier (VC)
video_out_tkeep[n/8-1:0] Output Specifies valid bytes
video_out_tlast Output End of line
video_out_tready Input Slave ready to accept data
video_out_tuser[n-1:0] Output
n is based on TUSER width selected in the Vivado IDE
95-80 CRC
(3)
79-72 ECC
71-70 Reserved
69-64 Data Type
63-48 Word Count
47-32 Line Number
31-16 Frame Number
15-2 Reserved
1 Packet Error
0 Start of frame
(2)
video_out_tvalid Output Data valid
Other Signals
csirxss_csi_irq Output Interrupt (active-High) from CSI-2 RX Controller
csirxss_iic_irq Output Interrupt (active-High) from AXI IIC
Table 2-5: Port Descriptions (Cont’d)
Signal Name Direction Description
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English