Xilinx ZCU106 User Manual

ZCU106 Board User Guide 111
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-49: J4 HPC1 FMC Section C and D Connections to XCZU7EV U1
J4
Pin
Schematic Net Name
I/O
Standard
U1
Pin
J4
Pin
Schematic Net Name I/O Standard
U1
Pin
C2 FMC_HPC1_DP0_C2M_P
(7)
AJ6 D1 VADJ_FMC_PGOOD (6)
C3 FMC_HPC1_DP0_C2M_N
(7)
AJ5 D4 FMC_HPC1_GBTCLK0_M2C_P
(1)(7)
Y8
C6 FMC_HPC1_DP0_M2C_P
(6)
AK4 D5 FMC_HPC1_GBTCLK0_M2C_N
(1)(6)
Y7
C7 FMC_HPC1_DP0_M2C_N
(7)
AK3 D8 FMC_HPC1_LA01_CC_P LVDS E24
C10 FMC_HPC1_LA06_P LVDS H21 D9 FMC_HPC1_LA01_CC_N LVDS D24
C11 FMC_HPC1_LA06_N LVDS H22 D11 FMC_HPC1_LA05_P LVDS G25
C14 FMC_HPC1_LA10_P LVDS F22 D12 FMC_HPC1_LA05_N LVDS G26
C15 FMC_HPC1_LA10_N LVDS E22 D14 FMC_HPC1_LA09_P LVDS G20
C18 FMC_HPC1_LA14_P LVDS D20 D15 FMC_HPC1_LA09_N LVDS F20
C19 FMC_HPC1_LA14_N LVDS D21 D17 FMC_HPC1_LA13_P LVDS C21
C22 NC D18 FMC_HPC1_LA13_N LVDS C22
C23 NC D20 NC
C26 NC D21 NC
C27 NC D23 NC
C30 FMC_HPC1_IIC_SCL
(2)
D24 NC
C31 FMC_HPC1_IIC_SDA
(2)
D26 NC
C34 GND D27 NC
C35 VCC12_SW D29 FMC_HPC1_TCK_BUF
(3)
C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF
(4)
C39 UTIL_3V3 D31 FMC_HPC1_TDO_HPC1_TDI
(3)(4)
D32 UTIL_3V3_10A
D33 FMC_HPC1_TMS_BUF
(3)
D34 NC
D35 GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 6 and 7.
3. FPGA U1 JTAG TCK, TMS, and TDO pins are buffered by U48 SN74AVC8T245.
4. J4 HPC1 TDO-TDI connections to U24 HPC1 FMC JTAG bypass switch (N.C. normally-closed/bypassing J4 until an FMC card
is plugged onto J4).
5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
6. U1 MGT (I/O standards do not apply).
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English