MC97F6108A User’s manual 14. 12-bit AD Converter (ADC)
Figure 65. ADC Operation Flow Sequence
14.4 Register map
Table 19. ADC Register Map
A/D Converter Mode Register
A/D Converter Data Low Register
A/D Converter Data High Register
A/D Converter Mode 1 Register
A/D Converter Mode 1 Register
Select ADC Clock & Data Align Bit.
ADC enable & Select AN Input Channel.
If Conversion is completed, AFLG is set “1” and ADC
interrupt is occurred.
After Conversion is completed, read ADCRH and ADCRL.