Abov MC97F6108A - Table of Contents

Contents MC97F6108A User’s manual
2
Contents
Introduction.............................................................................................................................................. 1
Reference document ............................................................................................................................... 1
1 Description ................................................................................................................................... 12
1.1 Device overview ................................................................................................................ 12
1.2 MC97F6108A block diagram ............................................................................................. 14
2 Pinouts and pin description .......................................................................................................... 15
2.1 Pinouts .............................................................................................................................. 15
2.2 Pin description ................................................................................................................... 17
3 Port structures .............................................................................................................................. 19
4 Memory organization .................................................................................................................... 22
4.1 Program memory............................................................................................................... 23
4.2 Data memory ..................................................................................................................... 24
4.3 External data memory ....................................................................................................... 26
4.4 SFR mapd ......................................................................................................................... 27
4.4.1 SFR map summary ............................................................................................... 27
4.4.2 SFR map............................................................................................................... 29
4.4.3 Compiler compatible SFR ..................................................................................... 34
5 I/O ports ....................................................................................................................................... 36
5.1 Port register ....................................................................................................................... 36
5.1.1 Data Register (Px) ................................................................................................ 36
5.1.2 Direction Register (PxIO) ...................................................................................... 36
5.1.3 Pull-up Register Selection Register (PxPU) ......................................................... 36
5.1.4 Open-drain Selection Register (PxOD) ................................................................ 36
5.1.5 De-bounce Enable Register (PxDB) ..................................................................... 36
5.1.6 Port Selection Register (psrx)............................................................................... 36
5.1.7 Register map ........................................................................................................ 37
5.2 P0 port ............................................................................................................................... 38
5.2.1 P0 port description ................................................................................................ 38
5.2.2 Register description for P0 ................................................................................... 38
5.3 P1 port ............................................................................................................................... 42
5.3.1 P1 port description ................................................................................................ 42
5.3.2 Register description for P1 ................................................................................... 42
5.4 P2 port ............................................................................................................................... 44
5.4.1 P2 port description ................................................................................................ 44
5.4.2 Register description for P2 ................................................................................... 44
6 Interrupt controller ........................................................................................................................ 46
6.1 External interrupt ............................................................................................................... 48
6.2 Comparator Interrupt and Comparator Flag ...................................................................... 49
6.3 Block diagram .................................................................................................................... 50
6.4 Interrupt vector table ......................................................................................................... 51
6.5 Interrupt sequence ............................................................................................................ 52
6.6 Effective timing after controlling interrupt bit ..................................................................... 53
6.7 Multi-interrupt .................................................................................................................... 54
6.8 Interrupt enable accept timing ........................................................................................... 55
6.9 Interrupt service routine address ....................................................................................... 55
6.10 Saving/restore general purpose registers ......................................................................... 55
6.11 Interrupt timing .................................................................................................................. 56
6.12 Interrupt register overview ................................................................................................. 57