6.12.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ................................................. 57
6.12.2 Interrupt Priority Register (IP, IPH, IP1, IP1H, IP2, IP2H, IP3 and IP3H) ............ 57
6.12.3 External Interrupt Flag Enable Register (EIENAB) .............................................. 57
6.12.4 External Interrupt Flag Register (EIFLAG) ........................................................... 57
6.12.5 External Interrupt Flag Edge Register (EIEDGE) ................................................. 57
6.12.6 External Interrupt Polarity Register (EIPOLA) ...................................................... 57
6.12.7 External Interrupt Flag Both Edge Enable Register (EIBOTH) ............................ 57
6.12.8 Comparator Interrupt Flag Enable Register (CIENAB) ........................................ 58
6.12.9 Comparator Interrupt Flag Register (CIFLAG) ..................................................... 58
6.12.10 Comparator Interrupt Flag Edge Register (CIEDGE) ........................................... 58
6.12.11 Comparator Interrupt Polarity Flag Register (CIPOLA) ........................................ 58
6.12.12 Comparator Interrupt Flag Both Edge Enable Register (CIBOTH) ...................... 58
6.12.13 Comparator Flag Enable Register (CFENAB) ...................................................... 58
6.12.14 Comparator Flag Register (CFFLAG) .................................................................. 58
6.12.15 Comparator Flag Edge Register (CFEDGE) ........................................................ 59
6.12.16 Comparator Flag Polarity Register (CFPOLA) ..................................................... 59
6.12.17 Comparator Flag Both Edge Enable Register (CFBOTH) .................................... 59
6.12.18 Pin Change Interrupt Enable Register (PCI) ........................................................ 59
6.12.19 Register map ........................................................................................................ 60
6.12.20 Interrupt register description ................................................................................. 61
7 Clock generator ............................................................................................................................ 75
7.1 Clock generator block diagram ......................................................................................... 75
7.2 Register map ..................................................................................................................... 76
7.3 Register description .......................................................................................................... 76
8 Basic Interval Timer (BIT) ............................................................................................................ 77
8.1 BIT block diagram ............................................................................................................. 77
8.2 BIT register map ................................................................................................................ 77
8.3 BIT register description ..................................................................................................... 78
9 Watchdog Timer (WDT) ............................................................................................................... 79
9.1 WDT interrupt timing waveform ......................................................................................... 79
9.2 WDT block diagram ........................................................................................................... 80
9.3 Register map ..................................................................................................................... 80
9.4 Register description .......................................................................................................... 81
10 Timer0/1/2/3 ................................................................................................................................. 82
10.1 Capture and event counter source for timer0/1/2/3 and PPG ........................................... 82
10.2 16-bit timer/counter mode ................................................................................................. 83
10.3 16-bit capture mode .......................................................................................................... 84
10.4 16-bit PWM mode.............................................................................................................. 85
10.5 Register map ..................................................................................................................... 88
10.6 Register description .......................................................................................................... 90
11 PPG (Programmable Pulse Generator) ....................................................................................... 94
11.1 PPG block diagram ........................................................................................................... 95
11.2 PPG start and one shot pulse ........................................................................................... 96
11.3 PPG period/duty write ....................................................................................................... 98
11.4 Capture mode .................................................................................................................... 99
11.5 Disable PPG output by comparator 1.............................................................................. 100
11.6 Disable PPG output by comparator 3.............................................................................. 101
11.7 PPG period limitation ...................................................................................................... 102
11.8 Auto period mode by comparator 2 ................................................................................. 103
11.8.1 PPG period decrease ......................................................................................... 104