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MC97F6108A
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Abov MC97F6108A - 20.20 Operating Voltage Range; 20.21 Recommended Circuit and Layout; Figure 115. Operating Voltage Range; Figure 116. Recommended Voltage Range
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20
.
Electrical ch
aracteristics
MC97F6108A Us
er’s manual
232
20.20
Operatin
g voltage range
2.7
5.5
16.0MHz
(f
IRC
= 16MHz)
Supply voltage (V)
Figure 11
5
.
Operat
ing Voltage
Range
20.21
Recommende
d circuit and layout
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Power
Figure 11
6
.
Recomme
nded Volta
ge Range
231
233
Table of Contents
Main Page
Default Chapter
1
Introduction
1
Reference Document
1
Table of Contents
2
1 Description
12
Device Overview
12
Table 1. MC97F6108A Device Features and Peripheral Counts
12
MC97F6108A Block Diagram
14
Figure 1. MC97F6108A Block Diagram
14
2 Pinouts and Pin Description
15
Pinouts
15
Figure 2. MC97F6108A 20 SOP Pin Assignment
15
Figure 3. MC97F6108A 16 SOPN Pin Assignment
16
Pin Description
17
Table 2. Normal Pin Description
17
3 Port Structures
19
Figure 4. General Purpose I/O Port
19
Figure 5. Secondary Function I/O Port
20
Figure 6. Analog Input I/O Port
21
4 Memory Organization
22
Program Memory
23
Figure 7. Program Memory Map
23
Data Memory
24
Figure 8. Data Memory Map
24
Figure 9. Lower 128Bytes of RAM
25
External Data Memory
26
Figure 10. XDATA Memory Area
26
SFR Mapd
27
SFR Map Summary
27
Table 3. SFR Map Summary
27
Table 4. XSFR Map Summary
28
SFR Map
29
Table 5. SFR Map
29
Table 6. XSFR Map
33
Compiler Compatible SFR
34
5 O Ports
36
Port Register
36
Data Register (Px)
36
Direction Register (Pxio)
36
Pull-Up Register Selection Register (Pxpu)
36
Open-Drain Selection Register (Pxod)
36
Bounce Enable Register (Pxdb)
36
Port Selection Register (Psrx)
36
Register Map
37
Table 7. Port Register Map
37
P0 Port
38
P0 Port Description
38
Register Description for P0
38
P1 Port
42
P1 Port Description
42
Register Description for P1
42
P2 Port
44
P2 Port Description
44
Register Description for P2
44
6 Interrupt Controller
46
Figure 11. Interrupt Group Priority Level
47
External Interrupt
48
Figure 12. External Interrupt Description
48
Comparator Interrupt and Comparator Flag
49
Figure 13. Comparator Interrupt and Comparator Flag Description
49
Block Diagram
50
Figure 14. Interrupt Controller Block Diagram
50
Interrupt Vector Table
51
Table 8. Interrupt Vector Address Table
51
Interrupt Sequence
52
Figure 15. Interrupt Sequence Flow
52
Effective Timing after Controlling Interrupt Bit
53
Figure 16. Effective Timing of Interrupt Enable Register
53
Figure 17. Effective Timing of Interrupt Flag Register
53
Multi-Interrupt
54
Figure 18. Effective Timing of Multi-Interrupt
54
Interrupt Enable Accept Timing
55
Interrupt Service Routine Address
55
Saving/Restore General Purpose Registers
55
Figure 19. Interrupt Response Timing Diagram
55
Figure 20. Correspondence between Vector Table Address and the Entry Address of ISR
55
Figure 21. Saving/Restore Process Diagram and Sample Source
55
Interrupt Timing
56
Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
56
Interrupt Register Overview
57
Interrupt Enable Register (IE, IE1, IE2, and IE3)
57
Interrupt Priority Register (IP, IPH, IP1, IP1H, IP2, IP2H, IP3 and IP3H)
57
External Interrupt Flag Enable Register (EIENAB)
57
External Interrupt Flag Register (EIFLAG)
57
External Interrupt Flag Edge Register (EIEDGE)
57
External Interrupt Polarity Register (EIPOLA)
57
External Interrupt Flag both Edge Enable Register (EIBOTH)
57
Comparator Interrupt Flag Enable Register (CIENAB)
58
Comparator Interrupt Flag Register (CIFLAG)
58
Comparator Interrupt Flag Edge Register (CIEDGE)
58
Comparator Interrupt Polarity Flag Register (CIPOLA)
58
Comparator Interrupt Flag both Edge Enable Register (CIBOTH)
58
Comparator Flag Enable Register (CFENAB)
58
Comparator Flag Register (CFFLAG)
58
Comparator Flag Edge Register (CFEDGE)
59
Comparator Flag Polarity Register (CFPOLA)
59
Comparator Flag both Edge Enable Register (CFBOTH)
59
Pin Change Interrupt Enable Register (PCI)
59
6.12.19 Register Map
60
Table 9. Interrupt Register Map
60
6.12.20 Interrupt Register Description
61
7 Clock Generator
75
Clock Generator Block Diagram
75
Figure 23. Clock Generator Block Diagram
75
Register Map
76
Register Description
76
Table 10. Clock Generator Register Map
76
8 Basic Interval Timer (BIT)
77
BIT Block Diagram
77
BIT Register Map
77
Figure 24. Basic Interval Timer Block Diagram
77
Table 11. Basic Interval Timer Register Map
77
BIT Register Description
78
9 Watchdog Timer (WDT)
79
WDT Interrupt Timing Waveform
79
Figure 25. Watchdog Timer Interrupt Timing Waveform
79
WDT Block Diagram
80
Register Map
80
Figure 26. Watchdog Timer Block Diagram
80
Table 12. Watchdog Timer Register Map
80
Register Description
81
10 Timer0/1/2/3
82
Capture and Event Counter Source for Timer0/1/2/3 and PPG
82
Table 13. Capture and Event Counter Source
82
16-Bit Timer/Counter Mode
83
Figure 27. 16-Bit Timer/Counter Mode of Timer0/1/2/3
83
16-Bit Capture Mode
84
Figure 28. 16-Bit Capture Mode of Timer0/1/2/3
84
16-Bit PWM Mode
85
Table 14. PWM Frequency Vs. Resolution at 16Mhz
85
Figure 29. 16-Bit PWM Mode of Timer0/1/2/3
86
Figure 30. 16-Bit PWM Example at 16Mhz
86
Figure 31. 16-Bit PWM Example at 16Mhz (Period=Duty)
87
Register Map
88
Table 15. Register Map
88
Register Description
90
11 PPG (Programmable Pulse Generator)
94
PPG Block Diagram
95
Figure 32. PPG Block Diagram
95
PPG Start and One Shot Pulse
96
Figure 33. PPG Start and One Shot Pulse
97
PPG Period/Duty Write
98
Figure 34. PPG Period/Duty Write
98
Figure 35. PPG Period/Duty Load to Compare Registers
98
Capture Mode
99
Figure 36. Capture Mode
99
Disable PPG Output by Comparator 1
100
Figure 37. Disable PPG Output by Comparator 1
100
Figure 38. Disable PPG Output by Comparator 1 (C1_FLAG)
100
Disable PPG Output by Comparator 3
101
Figure 39. Disable PPG Output Block Diagram by Comparator 3
101
Figure 40. Disable PPG Output by Comparator 3 (C3_FLAG)
101
PPG Period Limitation
102
Figure 41. PPG Period Limitation
102
Auto Period Mode by Comparator 2
103
Figure 42. Auto Period Mode Block Diagram
103
Figure 43. Period Decrement Block Diagram in Auto Period Mode
104
Figure 44. Period Decrement in Auto Period Mode
104
PPG Period Decrease
104
Figure 45. Auto Period Mode Block Diagram (ATPSEL = 2'B00)
105
Figure 46. Auto Period Mode (ATPSEL = 2'B00)
105
PPG Period When ATPSEL = 2'B00
105
Figure 47. Auto Period Mode Block Diagram (ATPSEL = 2'B01)
106
Figure 48. Auto Period Mode (ATPSEL = 2'B01)
106
PPG Period When ATPSEL = 2'B01
106
Figure 49. Auto Period Mode Block Diagram (ATPSEL = 2'B1X)
107
PPG Period When ATPSEL = 2'B1X
107
Figure 50. Auto Period Mode (ATPSEL = 2'B1X)
108
Figure 51. PPG Period Block Diagram When Writing
109
PPG Period When Writing
109
Figure 52. PPG Period When Writing (ATPSEL = 2'B1X)
110
Figure 53. Max and Min Period Limitation
111
PPG Period Min/Max Limitation
111
Figure 54. PPG Period Block Diagram When Period Min/Max Matching
112
Figure 55. When Max Period Matching
112
Figure 56. When Min Period Matching
113
Figure 57. PPG Off-Time Max/Min Limitation Block Diagram
114
PPG Off-Time Max/Min Limitation
114
Figure 58. PPG Off-Time Max/Min Limitation
115
Register Map
116
Table 16. Register Map
116
11.10 Register Description
117
12 Analog Comparator and OP-AMP
125
Comparator and OP-AMP Description
126
Block Diagram
128
Figure 59. Analog Comparator and OP-AMP Block Diagram
128
Register Description
129
13 Buzzer Driver
136
Table 17. Buzzer Frequency at 1Mhz
137
Buzzer Driver Block Diagram
138
Register Map
138
Figure 60. Buzzer Driver Block Diagram
138
Table 18. Buzzer Driver Register Map
138
Register Description
139
12 Bit AD Converter (ADC)
140
Conversion Timing
140
Block Diagram
140
Figure 61. 12-Bit ADC Block Diagram
141
Figure 62. A/D Analog Input Pin with a Capacitor
141
Figure 63. A/D Power (AVREF) Pin with a Capacitor
141
ADC Operation
142
Figure 64. Control Registers and Align Bits
142
Register Map
143
Figure 65. ADC Operation Flow Sequence
143
Table 19. ADC Register Map
143
Register Description
144
15 Usart
147
Block Diagram
148
Figure 66. USART Block Diagram
148
Clock Generation
149
Figure 67. Clock Generation Block Diagram
149
Table 20. Equations for Calculating Baud Rate Register Setting
149
External Clock (XCK)
150
Synchronous Mode Operation
150
Figure 68. Synchronous Mode XCK Timing
150
Data Format
151
Figure 69. a Frame Format
151
Parity Bit
152
USART Transmitter
152
Sending Tx Data
152
Transmitter Flag and Interrupt
152
Parity Generator
153
Disabling Transmitter
153
USART Receiver
153
Receiving Rx Data
153
Receiver Flag and Interrupt
154
Parity Checker
154
Disabling Receiver
155
Asynchronous Data Reception
155
Figure 70. Start Bit Sampling
155
Figure 71. Sampling of Data and Parity Bit
156
Figure 72. Stop Bit Sampling and Next Start Bit Sampling
156
SPI Mode
157
SPI Clock Formats and Timing
157
Table 21. CPOL Functionality
157
Figure 73. SPI Clock Formats When UCPHA = 0
158
Figure 74. SPI Clock Formats When UCPHA = 1
159
15.10 Register Map
160
Table 22. USART Register Map
160
15.11 Register Description
161
Baud Rate Settings (Example)
166
Table 23. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
166
16 Inter Integrated Circuit (I2C)
168
Block Diagram
168
Figure 75. I2C Block Diagram
168
I2C Bit Transfer
169
Start/ Repeated Start/ Stop
169
Figure 76. Bit Transfer on the I2C-Bus
169
Figure 77. START and STOP Condition
169
Data Transfer
170
Figure 78. Data Transfer on the I2C-Bus
170
Acknowledge
171
Figure 79. Acknowledge on the I2C-Bus
171
Synchronization/ Arbitration
172
Figure 80. Clock Synchronization During Arbitration Procedure
172
Figure 81. Arbitration Procedure of Two Masters
172
Block Operation
173
I2C Block Initialization Process
174
I2C Interrupt Service
175
Master Transmitter
176
Slave Receiver
178
Register Map
179
Table 24. Register Map
179
I2C Register Description
180
17 Power down Operation
184
Peripheral Operation in IDLE/ STOP Mode
184
Table 25. Peripheral Operation Status During Power down Mode
184
IDLE Mode
185
Figure 82. IDLE Mode Release Timing by an External Interrupt
185
Figure 83. IDLE Mode Release Timing by an RESETB
185
STOP Mode
186
Figure 84. STOP Mode Release Timing by External Interrupt
186
Figure 85. STOP Mode Release Timing by RESETB
187
Released Operation of STOP Mode
188
Figure 86. STOP1, 2 Mode Release Flow
188
Register Map
189
Register Description
189
Table 26. Power down Operation Register Map
189
18 Reset
190
Reset Block Diagram
190
Figure 87. Reset Block Diagram
190
Table 27. Hardware Setting Values in Reset State
190
RESET Noise Canceller
191
Power on Reset
191
Figure 88. Reset Noise Canceller Time Diagram
191
Figure 89. Fast VDD Rising Time
191
Figure 90. Internal RESET Release Timing on Power-Up
192
Figure 91. Configuration Timing When Power-On
192
Figure 92. Boot Process Waveform
193
Table 28. Boot Process Description
193
External RESETB Input
194
Figure 93. Timing Diagram after RESET
194
Figure 94. Oscillator Generating Waveform Example
194
Brown out Detector Processor
195
Figure 95. BOD Block Diagram
195
Figure 96. Internal Reset at Power Fail Situation
195
Register Map
196
Figure 97. Configuration Timing When LVR RESET
196
Table 29. Reset Operation Register Map
196
Register Description for Reset Operation
197
19 Memory Programming
199
Flash Control and Status Registers
199
Register Map
199
Table 30. Flash Control and Status Register Map
199
Register Description
200
Figure 98. Read Device Internal Checksum (Full Size: 0X0000~0X1Fff)
204
Table 31. Program and Erase Time
205
Memory Map
206
Flash Memory Map
206
Figure 99. Flash Memory Map
206
Figure 100. Address Configuration of Flash Memory
206
Serial In-System Program Mode
207
Flash Operation
207
Figure 101. the Sequence of Page Program and Erase of Flash Memory
207
Figure 102. the Sequence of Bulk Erase of Flash Memory
208
Table 32. Operation Mode
213
Parallel Mode
214
Figure 103. Pin Diagram for Parallel Programming
214
Table 33. Selection of Memory Type by ADDRH[7:4]
214
Parallel Mode Instruction Format
215
Table 34. Parallel Mode Instruction Format
215
Figure 104. Parallel Byte Read Timing of Program Memory
216
Figure 105. Parallel Byte Write Timing of Program Memory
216
Parallel Mode Timing Diagram
216
Mode Entrance Method of ISP Mode
217
Mode Entrance Method for ISP
217
Mode Entrance of Byte-Parallel
217
Figure 106. ISP Mode
217
Figure 107. Byte-Parallel Mode
217
Table 35. Mode Entrance Method for ISP
217
Table 36. Mode Entrance of Byte-Parallel
217
Security
218
Table 37. Security Policy Using Lock Bits
218
Configure Option
219
20 Electrical Characteristics
220
Absolute Maximum Ratings
220
Recommended Operating Conditions
220
Table 38. Absolute Maximum Ratings
220
Table 39. Recommended Operating Conditions
220
Internal RC Oscillator Characteristics
221
Internal WDT Oscillator Characteristics
221
Voltage Dropout Converter Characteristics
221
Table 40. Internal RC Oscillator Characteristics
221
Table 41. Internal WDT Oscillator Characteristics
221
Table 42. Voltage Dropout Converter Characteristics
221
A/D Converter Characteristics
222
Low Voltage Reset Characteristics
222
Table 43. A/D Converter Characteristics
222
Table 44. Low Voltage Reset Characteristics
222
Brown out Detector Characteristics
223
Power on Reset Characteristics
223
Table 45. Brown out Detector Characteristics
223
Table 46. Power-On Reset Characteristics
223
DC Characteristics
224
Table 47. DC Characteristics
224
20.11 AC Characteristics
225
Figure 108. AC Timing
225
Table 48. AC Characteristics
225
20.12 Analog Comparator Characteristics
226
20.13 Operational Amplifier Characteristics
226
Table 49. Analog Comparator DC Characteristics
226
Table 50. Operational Amplifier Characteristics
226
20.14 USART Characteristics
227
Figure 109. Waveform for USART Timing Characteristics
227
Figure 110. Timing Waveform for the USART Module
227
Table 51. USART Characteristics
227
20.15 SPI Characteristics
228
Figure 111. SPI Timing
228
Table 52. SPI Characteristics
228
20.16 I2C Characteristics
229
Figure 112. I2C Timing
229
Table 53. I2C Characteristics
229
20.17 Data Retention Voltage in STOP Mode
230
Figure 113. STOP Mode Release Timing When Initiated by an Interrupt
230
Figure 114. STOP Mode Release Timing When Initiated by RESETB
230
Table 54. Data Retention Voltage in STOP Mode
230
20.18 Internal Flash ROM Characteristics
231
20.19 Input/Output Capacitance
231
Table 55. Internal Flash ROM Characteristics
231
Table 56. Input/Output Capacitance
231
20.20 Operating Voltage Range
232
20.21 Recommended Circuit and Layout
232
Figure 115. Operating Voltage Range
232
Figure 116. Recommended Voltage Range
232
20.22 Typical Characteristics
233
Figure 117. Output High Voltage (VOH)
233
Figure 118. Output Low Voltage (VOL)
234
21 Package Information
235
20 SOP Package Information
235
Figure 119. 20 SOP Package Outline
235
16 SOPN Package Information
236
Figure 120. 16 SOPN Package Outline
236
22 Ordering Information
237
Figure 121. MC97F6108A Device Numbering Nomenclature
237
Table 57. MC97F6108A Device Ordering Information
237
23 Development Tools
238
Compiler
238
OCD II (On-Chip Debugger II) Emulator and Debugger
238
Programmers
239
Figure 122. Debugger (OCD1/OCD2) and Pinouts
239
Figure 123. E-PGM+ (Single Writer) and Pinouts
239
Figure 124. E-Gang4 and E-Gang6 (for Mass Production)
240
Gang Programmer
240
OCD II Emulator
240
Flash Programming
241
On-Board Programming
241
Table 58. Pins for Flash Programming
241
Circuit Design Guide
242
Figure 125. PCB Design Guide for On-Board Programming
242
On-Chip Debug System
243
Table 59. OCD II Features
243
Figure 126. On-Chip Debugging System in Block Diagram
244
Figure 127. 10-Bit Transmission Packet
245
Two-Pin External Interface
245
Figure 128. Data Transfer on Twin Bus
246
Figure 129. Bit Transfer on Serial Bus
246
Figure 130. Start and Stop Condition
246
Figure 131. Acknowledge on Serial Bus
247
Figure 132. Clock Synchronization During Wait Procedure
247
Figure 133. Connection of Transmission
248
Appendix
249
Instruction Table
249
Table 60. Instruction Table: Arithmetic
249
Table 61. Instruction Table: Logical
250
Table 62. Instruction Table: Data Transfer
251
Table 63. Instruction Table: Boolean
252
Table 64. Instruction Table: Branching
253
Table 65. Instruction Table: Miscellaneous
254
Table 66. Instruction Table: Additional Instructions
254
Revision History
255
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