Abov MC97F6108A User Manual

MC97F6108A User’s manual 15. USART
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15.9 SPI mode
USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the
following features.
 Full duplex, three-wire synchronous data transfer
 Master or Slave operation
 Supports all four SPI modes of operation (mode0, 1, 2, and 3)
 Selectable LSB first or MSB first data transfer
 Double buffered transmit and receive
 Programmable transmit bit rate
When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS) pin becomes active low input in
slave mode operation, or can be output in master mode operation if SPISS bit is set.
Remember that during SPI mode of operation, the pin RXD is renamed as MISO, and TXD is renamed
as MOSI for compatibility to other SPI devices.
15.9.1 SPI clock formats and timing
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the
USART has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four
clock formats for data transfers. UCPOL selectively inserts an inverter in series with a clock. UCPHA
selects one of two different clock phase relationships between the clock and the data. Note that UCPHA
and UCPOL bits in UCTRL1 register have different meanings according to the UMSEL[1:0] bits which
decides the operating mode of USART.
Table 21 shows four combinations of UCPOL and UCPHA for SPI mode 0, 1, 2, and 3.
Table 21. CPOL Functionality
SPI Mode
UCPOL
UCPHA
Leading Edge
Trailing Edge
0
0
0
Sample (Rising)
Setup (Falling)
1
0
1
Setup (Rising)
Sample (Falling)
2
1
0
Sample (Falling)
Setup (Rising)
3
1
1
Setup (Falling)
Sample (Rising)

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English