6.12 Interrupt register overview
6.12.1 Interrupt Enable Register (IE, IE1, IE2, and IE3)
Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits.
Total 23 peripherals are able to control interrupt.
6.12.2 Interrupt Priority Register (IP, IPH, IP1, IP1H, IP2, IP2H, IP3 and IP3H)
23 interrupts are divided into 6 groups which have 4 interrupt sources respectively. A group can be
assigned to 4 levels of interrupt priority using interrupt priority register. Level 3 is the highest priority,
while level 0 is the lowest priority.
After a reset, IPx and IPxH are cleared to ‘00H’. If interrupts have the same priority level, lower number
interrupt is served first.
6.12.3 External Interrupt Flag Enable Register (EIENAB)
External Interrupt Flag Enable Register (EIENAB) determined to enable each external interrupt to occur
by writing ‘1’. Also, these flags can be cleared to disable external interrupt by writing ‘0’ on to themselves.
6.12.4 External Interrupt Flag Register (EIFLAG)
External Interrupt Flag Register (EIFLAG) is set to ‘1’ when the pin changeable interrupt or the external
interrupt generating condition is satisfied while EIENAB is set to ‘1’. These flags are cleared when the
interrupt service routine is executed. Alternatively, these flags can be cleared by writing ‘0’ on to
themselves.
6.12.5 External Interrupt Flag Edge Register (EIEDGE)
External Interrupt Flag Edge Register (EIEDGE) determined a level or an edge type of external interrupt.
6.12.6 External Interrupt Polarity Register (EIPOLA)
External Interrupt Polarity Register (EIPOLA) determines a level type from high and low level or
determined an edge type from rising and falling edge. Initially, default value is to occur interrupt at high
level or rising edge.
6.12.7 External Interrupt Flag Both Edge Enable Register (EIBOTH)
External Interrupt Flag Both Edge Enable Register (EIBOTH) determines to enable the corresponding
external interrupt to occur by both edges (no level). And the value of EIEDGE and EIPOLA register are
ignored.
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