Abov MC97F6108A User Manual

MC97F6108A User’s manual 15. USART
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15 USART
Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible
serial communication device. USART of MC97F6108A features the followings:
 Full Duplex Operation (Independent Serial Receive and Transmit Registers)
 Asynchronous or Synchronous Operation
 Master or Slave Clocked Synchronous and SPI Operation
 Supports all four SPI Modes of Operation (Mode 0, 1, 2, 3)
 LSB First or MSB First Data Transfer @SPI mode
 High Resolution Baud Rate Generator
 Supports Serial Frames with 5,6,7,8, or 9 Data bits and 1 or 2 Stop bits
 Odd or Even Parity Generation and Parity Check Supported by Hardware
 Data OverRun Detection
 Framing Error Detection
 Digital Low Pass Filter
 Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
 Double Speed Asynchronous Communication Mode
USART has three main parts such as a Clock Generator, Transmitter and Receiver.
Clock Generation logic consists of a synchronization logic for external clock input used by synchronous
or SPI slave operation, and a baud rate generator for asynchronous or master (synchronous or SPI)
operation.
Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for
handling different serial frame formats. Write buffer allows a continuous transfer of data without any
delay between frames.
Receiver is the most complex part of the USART module due to its clock and data recovery units.
Recovery unit is used for asynchronous data reception. In addition to the recovery unit, Receiver
includes a parity checker, a shift register, a two level receive FIFO (UDATA) and control logic. Receiver
supports the same frame formats as Transmitter and can detect Frame Error, Data OverRun and Parity
Errors.

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English