Abov MC97F6108A - Page 146

14. 12-bit AD Converter (ADC) MC97F6108A User’s manual
146
ADCM1 (A/D Converter Mode Register): 96H
7
6
5
4
3
2
1
0
EXTRG
TSEL2
TSEL1
TSEL0
-
ALIGN
CKSEL1
CKSEL0
STBY = 1
R/W(
R/W
R/W
R/W
-
R/W
R/W
R/W
STBY = 0
W
W
W
W
-
W
W
W
Initial value: 01H
EXTRG
A/D external Trigger
A/D conversion Start by external Trigger, and Stop by clearing this bit
0
A/D conversion Stop and External Trigger disable
1
External Trigger enable
TSEL[2:0]
A/D Trigger Source selection
TSEL2
TSEL1
TSEL0
Description
0
0
0
External Interrupt 0
0
0
1
External Interrupt 1
0
1
0
-
0
1
1
-
1
0
0
Timer0 interrupt
1
0
1
Timer1 interrupt
1
1
0
Timer2 interrupt
1
1
1
Timer3 interrupt
ALIGN
A/D Converter data align selection.
0
MSB align (ADCRH[7:0], ADCRL[7:4]), default
1
LSB align (ADCRH[3:0], ADCRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1
CKSEL0
ADC Clock
ADC VDD
0
0
fx/2
Test Only
0
1
fx/4, default
3V~5V
1
0
fx/8
2.7V~3V
1
1
fx/32
2.4V~2.7V
NOTES:
1. fx : system clock
2. ADC clock have to be used 3MHz under