Abov MC97F6108A - Block Diagram; Figure 66. USART Block Diagram

15. USART MC97F6108A User’s manual
148
15.1 Block diagram
Figure 66. USART Block Diagram
XCK
XCK
Control
Clock Sync
Logic
UBAUD
RXD/
MISO
TXD/
MOSI
Tx
Control
Rx
Control
Clock
Recovery
Data
Recovery
DOR/PE/FE
Checker
UDATA[0]
(Rx)
UDATA[1]
(Rx)
Parity
Generator
Stop bit
Generator
UDATA(Tx)
SS
SS
Control
RXC
TXC
UPM1
UPM0
USIZE2
USIZE1
USIZE0
UCPOL
UCTRL1
ADDRESS: FA
H
INITIAL VALUE: 0000_0000
B
UDRIE
TXCIE
RXCIE
TXE
RXE
U2X
UCTRL2
ADDRESS: FB
H
INITIAL VALUE: 0000_0000
B
LOOPS
SPISS
USBS
TX8
RX8
UCTRL3
ADDRESS: FC
H
INITIAL VALUE: 0000_-000
B
UDRE
TXC
RXC
WAKE
DOR
FE
PE
USTAT
ADDRESS: FD
H
INITIAL VALUE: 1000_0000
B
SCLK
Rx Interrupt
Tx Interrupt
I
n
t
e
r
n
a
l
B
u
s
L
i
n
e
UMSEL1&UMSEL0
Master
UPM1
UPM0
UMSEL0
Master
UMSEL[1:0]
Baud Rate Generator