14.3 ADC operation
In this section, control registers and align bits are introduced in Figure 64, and ADC operation flow
sequence is introduced in Figure 65.
Align bit set 0
ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4
ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
Align bit set 1
ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0
ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
ADCRL[7:0]
ADCRH[3:0]
ADCRH[7:4] bits are 0
ADCRH[7:0]
ADCRL[7:4]
ADCRL[3:0] bits are 0