Abov MC97F6108A User Manual

MC97F6108A User’s manual 9. Watchdog Timer (WDT)
79
9 Watchdog Timer (WDT)
Watchdog Timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise
or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction
detection can be used as either a CPU reset or an interrupt request. When the watchdog timer is not
being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
It is possible to use free running 8-bit timer mode (WDTRSON=’0’) or watch dog timer mode
(WDTRSON=’1’) by setting WDTCR[6] bit. If WDTCR[5] is set to ‘1’, the WDT counter value is cleared
and counts up. After 1 machine cycle, this bit is cleared to ‘0’ automatically.
The WDT consists of an 8-bit binary counter and a watchdog timer data register. When value of the 8-
bit binary counter is equal to the 8 bits of WDTCNT, an interrupt request flag is generated. This can be
used as a watchdog timer interrupt or a reset signal of CPU in accordance with a bit WDTRSON.
Input clock source of the WDT is BIT overflow. An interval between watchdog timer interrupts is decided
by BIT overflow period and WDTDR set value. The equation can be described as the followings:
WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTDR Value+1)
9.1 WDT interrupt timing waveform
Figure 25. Watchdog Timer Interrupt Timing Waveform
WDT
Clock Source
WDTCR[7:0]
WDTR[7:0]
WDTIF
Interrupt
WDTRESETB
WDTCL
Occur
WDTR  0000_0011b
Match
Detect
Counter Clear
RESET
0
1
2
3
0
1
2
3
0
1
2
n
3

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English