17.4  Released operation of STOP mode 
After STOP1, 2 mode is released, operation begins according to content of related interrupt register just 
before STOP mode starts (refer to Figure 86). If the global interrupt Enable Flag (IE.EA)is set to `1`, the 
STOP1, 2 mode is released by a certain interrupt of which interrupt enable flag is set to `1` and the 
CPU jumps to the relevant interrupt service routine. Even if the IE.EA bit is cleared to ‘0’, the STOP 
mode is released by the interrupt of which the interrupt enable flag is set to ‘1’. 
Corresponding Interrupt 
Enable Bit (IE, IE1, IE2, IE3)