Abov MC97F6108A - Serial In-System Programming (ISP) Mode

To Next Page

To Previous Page

MC97F6108A User’s manual 19. Memory programming

207

19.3 Serial in-system program mode

Serial in-system program uses the interface of debugger which uses two wires. Refer to 23.

Development tools in details about debugger.

19.3.1 Flash operation

Configuration (This Configuration is just used for the description below)

FEMR[4] & [1]

FEMR[5] & [1]

FEMR[2]

FECR[6]

FECR[7]

ERASE&VFY

PGM&VFY

OTPE

AEE

AEF

Figure 101. The Sequence of Page Program and Erase of Flash Memory

Page Buffer Reset

Page Buffer Load (0X00H)

Erase

Erase Latency (500us)

Page Buffer Reset

Configuration Reg. setting

Cell Read

Pass/Fail?

Page Buffer Reset

Page Buffer Load

Program

Pgm Latency (500us)

Page Buffer Reset

Configuration Reg. setting

Cell Read

Yes

Pass/Fail?

Configuration Reg. Clear

Master Reset

In the case of OTP

OTPE flag Set

In the case of OTP

OTPE flag Set

Main Page

Default Chapter1
- Introduction1
- Reference Document1
- Table of Contents2
1 Description12
- Device Overview12
- Table 1. MC97F6108A Device Features and Peripheral Counts12
- MC97F6108A Block Diagram14
- Figure 1. MC97F6108A Block Diagram14
2 Pinouts and Pin Description15
- Pinouts15
- Figure 2. MC97F6108A 20 SOP Pin Assignment15
- Figure 3. MC97F6108A 16 SOPN Pin Assignment16
- Pin Description17
- Table 2. Normal Pin Description17
3 Port Structures19
- Figure 4. General Purpose I/O Port19
- Figure 5. Secondary Function I/O Port20
- Figure 6. Analog Input I/O Port21
4 Memory Organization22
- Program Memory23
- Figure 7. Program Memory Map23
- Data Memory24
- Figure 8. Data Memory Map24
- Figure 9. Lower 128Bytes of RAM25
- External Data Memory26
- Figure 10. XDATA Memory Area26
- SFR Mapd27
5 O Ports36
- Port Register36
- P0 Port38
  - P0 Port Description38
  - Register Description for P038
- P1 Port42
  - P1 Port Description42
  - Register Description for P142
- P2 Port44
  - P2 Port Description44
  - Register Description for P244
6 Interrupt Controller46
- Figure 11. Interrupt Group Priority Level47
7 Clock Generator75
- Clock Generator Block Diagram75
- Figure 23. Clock Generator Block Diagram75
- Register Map76
- Register Description76
- Table 10. Clock Generator Register Map76
8 Basic Interval Timer (BIT)77
- BIT Block Diagram77
- BIT Register Map77
- Figure 24. Basic Interval Timer Block Diagram77
- Table 11. Basic Interval Timer Register Map77
- BIT Register Description78
9 Watchdog Timer (WDT)79
- WDT Interrupt Timing Waveform79
- Figure 25. Watchdog Timer Interrupt Timing Waveform79
- WDT Block Diagram80
- Register Map80
- Figure 26. Watchdog Timer Block Diagram80
- Table 12. Watchdog Timer Register Map80
- Register Description81
10 Timer0/1/2/382
- Capture and Event Counter Source for Timer0/1/2/3 and PPG82
- Table 13. Capture and Event Counter Source82
- 16-Bit Timer/Counter Mode83
- Figure 27. 16-Bit Timer/Counter Mode of Timer0/1/2/383
- 16-Bit Capture Mode84
- Figure 28. 16-Bit Capture Mode of Timer0/1/2/384
- 16-Bit PWM Mode85
- Table 14. PWM Frequency Vs. Resolution at 16Mhz85
- Figure 29. 16-Bit PWM Mode of Timer0/1/2/386
- Figure 30. 16-Bit PWM Example at 16Mhz86
- Figure 31. 16-Bit PWM Example at 16Mhz (Period=Duty)87
- Register Map88
- Table 15. Register Map88
- Register Description90
11 PPG (Programmable Pulse Generator)94
- PPG Block Diagram95
- Figure 32. PPG Block Diagram95
- PPG Start and One Shot Pulse96
- Figure 33. PPG Start and One Shot Pulse97
- PPG Period/Duty Write98
- Figure 34. PPG Period/Duty Write98
- Figure 35. PPG Period/Duty Load to Compare Registers98
- Capture Mode99
- Figure 36. Capture Mode99
- Disable PPG Output by Comparator 1100
- Figure 37. Disable PPG Output by Comparator 1100
- Figure 38. Disable PPG Output by Comparator 1 (C1_FLAG)100
- Disable PPG Output by Comparator 3101
- Figure 39. Disable PPG Output Block Diagram by Comparator 3101
- Figure 40. Disable PPG Output by Comparator 3 (C3_FLAG)101
- PPG Period Limitation102
- Figure 41. PPG Period Limitation102
- Auto Period Mode by Comparator 2103
  - Figure 42. Auto Period Mode Block Diagram103
  - Figure 43. Period Decrement Block Diagram in Auto Period Mode104
  - Figure 44. Period Decrement in Auto Period Mode104
  - PPG Period Decrease104
  - Figure 45. Auto Period Mode Block Diagram (ATPSEL = 2'B00)105
  - Figure 46. Auto Period Mode (ATPSEL = 2'B00)105
  - PPG Period When ATPSEL = 2'B00105
  - Figure 47. Auto Period Mode Block Diagram (ATPSEL = 2'B01)106
  - Figure 48. Auto Period Mode (ATPSEL = 2'B01)106
  - PPG Period When ATPSEL = 2'B01106
  - Figure 49. Auto Period Mode Block Diagram (ATPSEL = 2'B1X)107
  - PPG Period When ATPSEL = 2'B1X107
  - Figure 50. Auto Period Mode (ATPSEL = 2'B1X)108
  - Figure 51. PPG Period Block Diagram When Writing109
  - PPG Period When Writing109
  - Figure 52. PPG Period When Writing (ATPSEL = 2'B1X)110
  - Figure 53. Max and Min Period Limitation111
  - PPG Period Min/Max Limitation111
  - Figure 54. PPG Period Block Diagram When Period Min/Max Matching112
  - Figure 55. When Max Period Matching112
  - Figure 56. When Min Period Matching113
  - Figure 57. PPG Off-Time Max/Min Limitation Block Diagram114
  - PPG Off-Time Max/Min Limitation114
  - Figure 58. PPG Off-Time Max/Min Limitation115
- Register Map116
- Table 16. Register Map116
- 11.10 Register Description117
12 Analog Comparator and OP-AMP125
- Comparator and OP-AMP Description126
- Block Diagram128
- Figure 59. Analog Comparator and OP-AMP Block Diagram128
- Register Description129
13 Buzzer Driver136
- Table 17. Buzzer Frequency at 1Mhz137
12 Bit AD Converter (ADC)140
- Conversion Timing140
- Block Diagram140
- Figure 61. 12-Bit ADC Block Diagram141
- Figure 62. A/D Analog Input Pin with a Capacitor141
- Figure 63. A/D Power (AVREF) Pin with a Capacitor141
- ADC Operation142
- Figure 64. Control Registers and Align Bits142
- Register Map143
- Figure 65. ADC Operation Flow Sequence143
- Table 19. ADC Register Map143
- Register Description144
15 Usart147
- Block Diagram148
- Figure 66. USART Block Diagram148
- Clock Generation149
- Figure 67. Clock Generation Block Diagram149
- Table 20. Equations for Calculating Baud Rate Register Setting149
- External Clock (XCK)150
- Synchronous Mode Operation150
- Figure 68. Synchronous Mode XCK Timing150
- Data Format151
- Figure 69. a Frame Format151
- Parity Bit152
- USART Transmitter152
- USART Receiver153
- SPI Mode157
- 15.10 Register Map160
- Table 22. USART Register Map160
- 15.11 Register Description161
- Baud Rate Settings (Example)166
- Table 23. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies166
16 Inter Integrated Circuit (I2C)168
- Block Diagram168
- Figure 75. I2C Block Diagram168
- I2C Bit Transfer169
- Start/ Repeated Start/ Stop169
- Figure 76. Bit Transfer on the I2C-Bus169
- Figure 77. START and STOP Condition169
- Data Transfer170
- Figure 78. Data Transfer on the I2C-Bus170
- Acknowledge171
- Figure 79. Acknowledge on the I2C-Bus171
- Synchronization/ Arbitration172
- Figure 80. Clock Synchronization During Arbitration Procedure172
- Figure 81. Arbitration Procedure of Two Masters172
- Block Operation173
- Register Map179
- Table 24. Register Map179
- I2C Register Description180
17 Power down Operation184
- Peripheral Operation in IDLE/ STOP Mode184
- Table 25. Peripheral Operation Status During Power down Mode184
- IDLE Mode185
- Figure 82. IDLE Mode Release Timing by an External Interrupt185
- Figure 83. IDLE Mode Release Timing by an RESETB185
- STOP Mode186
- Figure 84. STOP Mode Release Timing by External Interrupt186
- Figure 85. STOP Mode Release Timing by RESETB187
- Released Operation of STOP Mode188
- Figure 86. STOP1, 2 Mode Release Flow188
- Register Map189
- Register Description189
- Table 26. Power down Operation Register Map189
18 Reset190
- Reset Block Diagram190
- Figure 87. Reset Block Diagram190
- Table 27. Hardware Setting Values in Reset State190
- RESET Noise Canceller191
- Power on Reset191
- Figure 88. Reset Noise Canceller Time Diagram191
- Figure 89. Fast VDD Rising Time191
- Figure 90. Internal RESET Release Timing on Power-Up192
- Figure 91. Configuration Timing When Power-On192
- Figure 92. Boot Process Waveform193
- Table 28. Boot Process Description193
- External RESETB Input194
- Figure 93. Timing Diagram after RESET194
- Figure 94. Oscillator Generating Waveform Example194
- Brown out Detector Processor195
- Figure 95. BOD Block Diagram195
- Figure 96. Internal Reset at Power Fail Situation195
- Register Map196
- Figure 97. Configuration Timing When LVR RESET196
- Table 29. Reset Operation Register Map196
- Register Description for Reset Operation197
19 Memory Programming199
- Flash Control and Status Registers199
- Memory Map206
- Serial In-System Program Mode207
- Parallel Mode214
- Mode Entrance Method of ISP Mode217
- Security218
- Table 37. Security Policy Using Lock Bits218
- Configure Option219
20 Electrical Characteristics220
- Absolute Maximum Ratings220
- Recommended Operating Conditions220
- Table 38. Absolute Maximum Ratings220
- Table 39. Recommended Operating Conditions220
- Internal RC Oscillator Characteristics221
- Internal WDT Oscillator Characteristics221
- Voltage Dropout Converter Characteristics221
- Table 40. Internal RC Oscillator Characteristics221
- Table 41. Internal WDT Oscillator Characteristics221
- Table 42. Voltage Dropout Converter Characteristics221
- A/D Converter Characteristics222
- Low Voltage Reset Characteristics222
- Table 43. A/D Converter Characteristics222
- Table 44. Low Voltage Reset Characteristics222
- Brown out Detector Characteristics223
- Power on Reset Characteristics223
- Table 45. Brown out Detector Characteristics223
- Table 46. Power-On Reset Characteristics223
- DC Characteristics224
- Table 47. DC Characteristics224
- 20.11 AC Characteristics225
- Figure 108. AC Timing225
- Table 48. AC Characteristics225
- 20.12 Analog Comparator Characteristics226
- 20.13 Operational Amplifier Characteristics226
- Table 49. Analog Comparator DC Characteristics226
- Table 50. Operational Amplifier Characteristics226
- 20.14 USART Characteristics227
- Figure 109. Waveform for USART Timing Characteristics227
- Figure 110. Timing Waveform for the USART Module227
- Table 51. USART Characteristics227
- 20.15 SPI Characteristics228
- Figure 111. SPI Timing228
- Table 52. SPI Characteristics228
- 20.16 I2C Characteristics229
- Figure 112. I2C Timing229
- Table 53. I2C Characteristics229
- 20.17 Data Retention Voltage in STOP Mode230
- Figure 113. STOP Mode Release Timing When Initiated by an Interrupt230
- Figure 114. STOP Mode Release Timing When Initiated by RESETB230
- Table 54. Data Retention Voltage in STOP Mode230
- 20.18 Internal Flash ROM Characteristics231
- 20.19 Input/Output Capacitance231
- Table 55. Internal Flash ROM Characteristics231
- Table 56. Input/Output Capacitance231
- 20.20 Operating Voltage Range232
- 20.21 Recommended Circuit and Layout232
- Figure 115. Operating Voltage Range232
- Figure 116. Recommended Voltage Range232
- 20.22 Typical Characteristics233
- Figure 117. Output High Voltage (VOH)233
- Figure 118. Output Low Voltage (VOL)234
21 Package Information235
- 20 SOP Package Information235
- Figure 119. 20 SOP Package Outline235
- 16 SOPN Package Information236
- Figure 120. 16 SOPN Package Outline236
22 Ordering Information237
- Figure 121. MC97F6108A Device Numbering Nomenclature237
- Table 57. MC97F6108A Device Ordering Information237
23 Development Tools238
- Compiler238
- OCD II (On-Chip Debugger II) Emulator and Debugger238
- Programmers239
- Flash Programming241
- On-Chip Debug System243
Appendix249
- Instruction Table249
- Table 60. Instruction Table: Arithmetic249
- Table 61. Instruction Table: Logical250
- Table 62. Instruction Table: Data Transfer251
- Table 63. Instruction Table: Boolean252
- Table 64. Instruction Table: Branching253
- Table 65. Instruction Table: Miscellaneous254
- Table 66. Instruction Table: Additional Instructions254
- Revision History255

Abov MC97F6108A - Serial In-System Programming (ISP) Mode

Table of Contents

Related product manuals