Abov MC97F6108A - Interrupt Enable Accept Timing; Interrupt Service Routine Address; SavingRestore General Purpose Registers; Figure 19. Interrupt Response Timing Diagram

MC97F6108A User’s manual 6. Interrupt controller
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6.8 Interrupt enable accept timing
Figure 19. Interrupt Response Timing Diagram
6.9 Interrupt service routine address
Figure 20. Correspondence between Vector Table Address and the Entry Address of ISR
6.10 Saving/restore general purpose registers
Figure 21. Saving/Restore Process Diagram and Sample Source
Interrupt
latched
Interrupt
goes
active
System
Clock
Max. 4 Machine Cycle
4 Machine Cycle
Interrupt Processing
: LCALL & LJMP
Interrupt Routine
0E
2EH
0125H
0126H
Basic Interval Timer
Service Routine Address
Basic Interval Timer
Vector Table Address
00B3H
00B4H
02H
25H
01H
00B5H