Abov MC97F6108A User Manual

MC97F6108A User’s manual 6. Interrupt controller
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Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-
trigger mode. Figure 11 shows the Interrupt Group Priority Level that is available for sharing interrupt
priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IPx, another one
from IPxH). Each bit of IPx and IPxH corresponds to each interrupt and decides one of 4 priority levels
of each interrupt. Interrupt service routine serves higher priority interrupt first. If two requests of different
priority levels are received simultaneously, the request of higher priority level is served prior to the lower
one.
level 0
INT0 INT1 INT2 INT3 INT5 INT6 INT7 INT8 INT9 INT11 INT12 INT13 INT14 INT15
level 1
level 2
level 3
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
IPxH
IPx
( IP, IPH ) ( IP1, IP1H ) ( IP2, IP2H )
high low
high
low
INT4
INT10
IP0H.0 IP0H.1 IP0H.2 IP0H.3 IP0H.4 IP0H.5 IP1H.0 IP1H.1 IP1H.2 IP1H.3 IP1H.4 IP1H.5 IP2H.0 IP2H.1 IP2H.2 IP2H.3
IP0.0 IP0.1 IP0.2 IP0.3 IP0.4 IP0.5 IP1.0 IP1.1 IP1.2 IP1.3 IP1.4 IP1.5 IP2.0 IP2.1 IP2.2 IP2.3
INT16 INT17
0 0
0 0
IP2H.4 IP2H.5
IP2.4 IP2.5
INT18 INT20 INT21
0 1 0 0
0 0 0 0
( IP3, IP3H )
IP3H.0 IP3H.1 IP3H.2 IP3H.3
IP3.0 IP3.1 IP3.2 IP3.3
INT22 INT23
0 0
0 0
IP3H.4 IP3H.5
IP3.4 IP3.5
INT19
Figure 11. Interrupt Group Priority Level

Abov MC97F6108A Specifications

General

Brand	Abov
Model	MC97F6108A
Category	Microcontrollers
Language	English