MC97F6108A User’s manual 4. Memory organization
4.4.2 SFR map
Table 5. SFR Map
Data Pointer Register Low
Data Pointer Register High
Data Pointer Register Low 1
Data Pointer Register High 1
Reset Source Flag register
System and Clock Control Register
BIT Clock Control Register
Basic Interval Timer Register
Watch Dog Timer Mode Register
Watch Dog Timer Counter Register
Interrupt Priority Register
Interrupt Priority Register High
Pin Change Interrupt Enable Register
A/D Converter Mode Register
A/D Converter Result Low Register
A/D Converter Mode 1 Register(STBY=1)
A/D Converter Mode 1 Register(STBY=0)
A/D Converter Result High Register
Interrupt Priority Register 1
Interrupt Priority Register 1 High
Interrupt Priority Register 2
Interrupt Priority Register 2 High
Interrupt Priority Register 3
Interrupt Priority Register 3 High
Comparator Flag Both Edge Enable
Register
Extended Operation Register
External Interrupt Flag Enable Register
External Interrupt Flag Register
External Interrupt Flag Edge Register