Figure 73. SPI Clock Formats when UCPHA = 0
When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes
to active low. The first XCK edge causes both the master and the slave to sample the data bit value on
their MISO and MOSI inputs, respectively.
At the second XCK edge, the USART shifts the second data bit value out to the MOSI and MISO outputs
of the master and slave, respectively. Unlike the case of UCPHA=1, when UCPHA=0, the slave’s SS
input must go to its inactive high level between transfers. This is because the slave can prepare the first
data bit when it detects falling edge of SS input.
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