MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C)
I2CSR (I2C Status Register): DBH
This bit has different meaning depending on whether I2C is master or
slave. Note 1)
When I2C is a master, this bit represents whether it received AACK
(Address ACK) from slave.
When I2C is a slave, this bit is used to indicate general call.
No AACK is received (Master mode)
AACK is received (Master mode)
Received address is not general call address (Slave mode)
General call address is detected (Slave mode)
This bit is set when 1-Byte of data is transferred completely. Note 1)
1byte of data is not completely transferred
1byte of data is completely transferred
This bit is set when STOP condition is detected. Note 1)
No STOP condition is detected
STOP condition is detected
This bit is set when I2C is addressed by other master. Note 1)
I2C is not selected as slave
I2C is addressed by other master and acts as a slave
This bit represents the result of bus arbitration in master mode. Note 1)
I2C maintains bus mastership
I2C has lost bus mastership during arbitration process
This bit reflects bus status.
I2C bus is idle, so any master can issue a START condition
This bit is used to indicate whether I2C is transmitter or receiver.
This bit shows the state of ACK signal.
ACK is generated at ninth SCL period
NOTES:
1. One of these bits can be a source of an interrupt.
2. When an I2C interrupt occurs except for STOP interrupt, the SCL line is hold LOW.
To release SCL, write arbitrary value to I2CSR.
3. When I2CSR is written, the TEND, STOP, SSEL, LOST, RXACK bits are cleared.
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